參數(shù)資料
型號(hào)： PONE-000-01
廠商： Electronic Theatre Controls, Inc.
英文描述： The ideal device for simple nodes, such as switches, actuators and sensor
中文描述： 在簡(jiǎn)單的節(jié)點(diǎn)，如交換機(jī)，執(zhí)行器和傳感器的理想設(shè)備
文件頁(yè)數(shù)： 20/56頁(yè)
文件大?。?/td> 432K
代理商： PONE-000-01
March 2000
CEWay
PL-One Data Sheet
D-CW-0100-04
Page 20 of 56
State
Description
Transition
The SES will go back to IDLE if the Ph_Request_Reg
tx
bit is cleared.
XMIT_SYM State
The PLSE Sublayer is in the process of transmitting symbols. The
symbols are received from the PL-One firmware, one byte at a time
through Ph_Tx_Buffer. Starting from LSB, the symbols are encoded as
transitions between the SUPERIOR 1 and SUPERIOR 2 states. When the
requested medium state lasts 1 UST, a “1” will be shifted into the CRC
computation register. When the requested medium state lasts 2 USTs, a
“0” will be shifted into the CRC computation register.
If the Ph_Request_Reg
lzs
bit was set, then none of the leading zeros in
Ph_Tx_Buffer will be transmitted. The Ph_Request_Reg
tx_del
1
and
tx_del
0
bits are used to select what type of delimiter (none, EOF, or EOP)
will be appended to the end of the byte transmission. The PEOF delimiter
is not available in this state.
An interrupt is sent to the PL-One firmware as soon as the information in
Ph_Request_Reg and Ph_Tx_Buffer has been copied to the SES’ internal
one-byte transmission buffers.
Transition
When the SES has finished transmitting an EOP symbol, it will go to
XMIT_CRC.
Transition
The SES will stop transmitting and go back to IDLE if the Ph_Request_Reg
tx
bit is cleared.
XMIT_CRC State
The PLSE Sublayer is in the process of transmitting 16 CRC symbols. The
symbols are generated by the CRC polynomial from the preceding UST
values. A CRC bit value of 1 corresponds to the same SUPERIOR state
that was used to transmit the PEOF, while a bit value of 0 corresponds to
the alternative SUPERIOR symbol. CRC bits are transmitted most
significant bit first. For example, if the first Symbol transmitted is
SUPERIOR 2 (ie. the PEOF was encoded using SUPERIOR 2s), then a 1
in the CRC buffer = SUPERIOR 2 and 0 = SUPERIOR 1.
Action
Once the CRC has been completely transmitted, the SES will send an
interrupt to the PL-One firmware. It will also start providing the timestamp
to the PL-One firmware, and go to XMIT_STAMP.
Transition
The SES will stop transmitting and go back to IDLE if the Ph_Request_Reg
tx
bit is cleared.
XMIT_STAMP
State
The PLSES is in the process of providing the timestamp to PL-One
firmware. The timestamp is the time associated with the end of the CRC
transmission. The timestamp will be provided on four bytes (LSB first
followed by more significant bytes), where each byte will be sent to PL-One
firmware via interrupt in Ph_Rx_Buffer, and the Ph_Confirm_Reg
be/bf
bit
will be set. The timestamp is based on a free running counter, which is
incremented by the PLSES system clock (i.e. once every 279ns).
Transition
The SES will go back to IDLE when Ph_Request_Reg = 0.
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