參數(shù)資料
型號(hào): PSB7238
廠商: SIEMENS A G
元件分類: 編解碼器
英文描述: Joint Audio Decoder-Encoder - Multimode
中文描述: A/MU-LAW, PCM CODEC, PQFP100
文件頁(yè)數(shù): 117/190頁(yè)
文件大?。?/td> 2255K
代理商: PSB7238
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PSB 7238
Register Description
Semiconductor Group
117
Data Sheet 1998-07-01
Receive Status Register
This byte is the same as the byte appended in the RFIFO to the last byte (or CRC) of the
frame. The value is updated after the end flag has been received and before RSTA is
written to the RFIFO and RME interrupt status is generated.
The status register is completely reset with every start flag. Thus, the DSP/host should
always use the RSTA value from the RFIFO to evaluate the status at the end of the
corresponding frame, since the register contents does not necessarily refer to the current
frame being read from the RFIFO.
Has no meaning in transparent mode.
VFR
RSTA
Read
Address 21
H
Bit 7
VFR
Bit 0
RSTA
RDO
CRC
RAB
Valid Frame
Indicates whether the frame length is valid (1) or not (0).
Set:
If the frame length (transparent data without zero insertion) is a
multiple of 8 bits and the frame contains at least 16 bits.
Reset: All other frame lengths, with every new start flag
Receive Data Overflow
At least one byte of the frame has been lost because it could not be stored
in the FIFO.
Set:
When one byte of frame data is available from the HDLC bitengine
but cannot be stored in the RFIFO because it’s full.
Reset: With every new start flag
CRC check
Correct (1) or incorrect (0). The value is updated after the end flag has been
received and before RSTA is written to the RFIFO and RME interrupt status
is generated.
Set:
CRC correct
Reset: CRC incorrect, with every new start flag
Receive Message Aborted
Frame aborted by the remote station (7 consecutive ‘1’s received), yes (1)
or no (0).
Set:
After 7 consecutive ‘1’s have been received
Reset: With every new start flag
RDO
CRC
RAB
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