
PSB 7238
Register Description
Semiconductor Group
126
Data Sheet 1998-07-01
Transmit Channel Capacity Register
XCC
Interrupt Status Register
RME
XCCR
Read/Write
Address 2B
H
Bit 7
XCC7
Bit 0
XCC0
XCCR
XCC6
XCC5
XCC4
XCC3
XCC2
XCC1
Transmit Channel Capacity
Defines the number of bits in the transmit time-slot.
Number of bits = XCC + 1 (1
… 256 bits/time-slot).
ISR
Read
Address 2C
H
Bit 7
RME
Bit 0
ISR
RPF
RFO
XPR
XDU
ALLS
Receive Message End
One complete frame of length less than 32 bytes, or the last part of a frame
at least 32 bytes long is stored in the receive FIFO, including the status byte.
No RPF is generated in this case. The number of bytes stored is given by
RBC bits 0-4. Has no meaning in transparent mode.
Set:
When the last part of a frame has been transferred to the DSP/host
accessible part of RFIFO.
Reset: After ISR is read, after RRES, after hardware reset.
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame has not yet
been completely received. In transparent mode, signifies that 32 bytes can
be read from the FIFO.
Set:
When a part of a frame (but not the last part) has been transferred
to the DSP/host accessible part of RFIFO.
Reset: After ISR is read, after RRES, after hardware reset.
Receive Frame Overflow
Indicates that a frame has been lost because the FIFO was full at the
reception of the beginning of a frame. In transparent mode, signifies that
data has been lost because no room was available in RFIFO.
Set:
The DSP/host inaccessible part of RFIFO is full and the beginning
of a new frame is detected.
Reset: After ISR is read, after RRES, after hardware reset.
RPF
RFO