
PSB 7238
Register Description
Semiconductor Group
118
Data Sheet 1998-07-01
Mode Register
TMO
MODE
Read/Write
Address 22
H
Bit 7
TMO
Bit 0
ETFS
MODE
RAC
XAC
TLP
ERFS
Transparent Mode
A ‘1’ selects the transparent non-HDLC mode, where no HDLC framing
functions are implemented. In transparent mode, data reception and
transmission is started time-slot aligned.
Receiver Active
Sets the receiver in an active state, where the receiver goes into the hunt
mode
1)
(see
Page 127
).
Note:
In transparent mode, when RAC is set to ‘1’, storage of bytes in the
receive FIFO starts time-slot aligned.
Transmitter Active
When ‘1’, the HDLC transmitter transmits on the line and in the time-slot
assigned to it (interframe time-fill if no data is available). When XAC = 0, the
time-slot assigned to the transmitter is in high impedance.
Note:
In transparent mode, when XAC is set to ‘1’, transmission of bytes
from the transmit FIFO starts time-slot aligned.
Test Loop
When ‘1’, output of the HDLC controller is connected to input (i.e. what is
transmitted is simultaneously received). The loop is transparent.
Enable RFS generation
Only valid when RFIN = 0 (RFS pulses internally generated) and used if
RCONT bit in RFS mode register is ‘1’.
When RCONT = 1
, an ERFS value of ‘1’ enables the generation of RFS
pulses of one bit duration and spaced RPRD + 1 (1, …, 32) 16-bit words
from each other. Pulses are generated indefinitely until ERFS is set to ‘0’
again.
Enable TFS generation
Only valid when TFIN = 0 (TFS pulses internally generated) and used if
TCONT bit in TFS mode register is ‘1’.
When TCONT = 1
, an ETFS value of ‘1’ enables the generation of TFS
pulses of one bit duration and spaced TPRD + 1 (1, …, 32) 16-bit words
from each other. Pulses are generated indefinitely until ETFS is set to ‘0’
again.
RAC
XAC
TLP
ERFS
ETFS