
PSB 7238
Register Description
Semiconductor Group
99
Data Sheet 1998-07-01
Transmit Audio Channel 1
Read/Write
Address 2017
H
- 2019
H
Value after reset: 00
H
EN
Enable
If inactive (0), no clock is generated for this channel, and the channel is
in high impedance, must be set to 0 during configuration of transmit
audio channel 1.
Select Line
00
Channel time-slot on DU (frame sync FSC, clock DCL or DCL/2)
01
Channel time-slot on DD (frame sync FSC, clock DCL or DCL/2)
10
Channel time-slot on SR (frame sync RFS, clock SCLK)
11
Channel time-slot on ST (frame sync TFS, clock SCLK)
Length of channel time-slot
Channel time-slot length in bits = LEN + 1 (1,
…, 32 bits).
Time-slot position
Position of first bit of time-slot from frame sync (0, …, 511).
Load Mode
0
Sample of length LEN + 1 loaded from write register into shift
register (
for frame + 1
) at the occurrence of frame sync.
1
When shift register is about to become empty
((LBIT + 1)
×
(LEN + 1) bits shifted out), it is loaded from write
register (for software to be accessed via a “Buffer Empty”
interrupt status).
Load Bits
Number of bits in aggregates of (LEN + 1) loaded into output shift
register when ready, if LMOD = 1. The number of bits loaded is equal to
(LBIT + 1)
×
(LEN + 1), the corresponding interrupt status is BEMP1.
Since the number of bits is 32 maximum, the value of the product
(LBIT + 1)
×
(LEN + 1) shall not exceed 32.
Host Transmit Access
0
Channel originates from DSP
1
Channel originates from Host
SLIN(1-0)
LEN(4-0)
TS(8-0)
LMOD
LBIT(4-0)
HXA