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參數(shù)資料
| 型號(hào)： | PSB7238 |
| 廠商： | SIEMENS A G |
| 元件分類： | 編解碼器 |
| 英文描述： | Joint Audio Decoder-Encoder - Multimode |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP100 |
| 文件頁(yè)數(shù)： | 51/190頁(yè) |
| 文件大?。?/td> | 2255K |
| 代理商： | PSB7238 |
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PSB 7238
Functional Blocks
Semiconductor Group
51
Data Sheet 1998-07-01
Audio Channel Transfer
As mentioned in
Section 3
, all the serial channels (2 receive audio, 2 transmit audio, and
two full-duplex HDLC/transparent data channels) can be transferred between one of the
serial interfaces and the DSP or the host in a flexible manner.
The interface to each of the audio channels is a 32-bit wide shift register. In receive
direction, when the shift register is filled to a programmable level (up to 32 bits), the
whole 32-bit shift register is loaded into the receive channel read register set accessible
from the DSP and from the host. Simultaneously, a maskable interrupt status is set.
Similarly, in the transmit direction, transmit channel data is loaded from the write register
pertaining to that channel (either from DSP or host register, as selected via a control bit)
into the transmit shift register when a selectable number of bits have been shifted out.
The buffering of up to 32 bits reduces the reaction time of the DSP software.
As an alternative to this, the audio channel data can also be loaded from the shift register
to the DSP/host registers (receive direction) and from the DSP/host registers into the
shift register (transmit direction) at the occurrence of the frame sync pulse. In this case
the number of significant bits in the registers is determined by the time-slot length
programmed on the receive/transmit line. The DSP/host has 125
μ
s to read/write the
register while new data is assembled or the contents of the shift register are transmitted,
during the following frame. (This option could be used for DSP software synchronized on
the 8-kHz time base).
The audio channel registers, each of length 2 words/4 bytes, are (see
Section 3
):
The relevant parameters for controlling the transfer of the audio channels are
(independent for each channel):
RC1
RC2
XC1
XC2
Receive channel 1.
Receive channel 2.
Transmit channel 1.
Transmit channel 2.
EN
LMOD
Enable channel.
Load mode (either once per frame, or after LBIT bits have been
received/transmitted).
Load bits. Gives the number of bits (1 to 32) to be loaded, in multiples of
the physical time-slot length.
LBIT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSB7280 | Joint Audio Decoder-Encoder |
| PSB8510-1P | Programmable Dialing Circuit |
| PSB8510-1T | Programmable Dialing Circuit |
| PSB8510-6P | Programmable Dialing Circuit |
| PSB8510-6T | Programmable Dialing Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSB7238FV2.1JADEMM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder |
| PSB7280FV3.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280FV3.1D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7300AGDW | 制造商:Infineon Technologies AG 功能描述: |
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