參數資料
型號： PSD813F
廠商： 意法半導體
英文描述： Flash In-System-Programmable Microcontroller Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程微控制器外圍設備（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數： 79/130頁
文件大小： 650K
代理商： PSD813F
Preliminary
PSD813F Family
The
PSD813F
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
Power On Reset
Upon power up the PSD813F requires a reset pulse of tNLNH-PO (minimum 1ms) after
V
CC
is steady. During this time period the device loads internal configurations, clears some
of the registers and sets the Flash or EEPROM into operating mode. After the rising edge of
reset, the PSD813F remains in the reset state for an additional tOPR (minimum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD813F Flash or EEPROM memory is reset to the read array mode upon power up.
The FSi and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove the
possibility of a byte being written on the first edge of a write strobe signal. The PSD
automatically prevents write strobes from reaching the EEPROM memory array for about
5 ms (tEEHWL). Any Flash memory write cycle initiation is prevented automatically when
V
CC
is below VLKO.
Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 33 shows the timing of the power on and warm reset.
75
OPERATING LEVEL
POWER ON RESET
V
CC
RESET
tNLNH–PO
tOPR
tNLNH
tOPR
WARM
RESET
Figure 33. Power On and Warm Reset Timing
I/O Pin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD status during power on reset, warm reset and
power down mode. PLD outputs are always valid during warm reset, and they are valid in
power on reset once the internal PSD configuration bits are loaded. This loading of PSD is
completed typically long before the V
CC
ramps up to operating level. Once the PLD is
active, the state of the outputs are determined by the PSDabel equations.
相關PDF資料
PDF描述
PSD813FH(中文) Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現場可編程微控制器)
PSD813FN(中文) Field Programmble Microcontroller Peripherals(帶閃存的現場可編程微控制器)
PSD813FN Field Programmble Microcontroller Peripherals(帶閃存的現場可編程微控制器)
PSD813FH Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現場可編程微控制器)
PSD82 Three Phase Rectifier Bridges
相關代理商/技術參數
參數描述
PSD813F1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1A 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V
PSD813F1-A 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1A-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1-A-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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