參數(shù)資料
型號: RIVA 128ZX
廠商: 意法半導體
英文描述: 128-Bit 3D Multimedia Accelerator(128位3D多媒體加速器)
中文描述: 128位3D多媒體加速器(128位三維多媒體加速器)
文件頁數(shù): 20/85頁
文件大?。?/td> 608K
代理商: RIVA 128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
20/85
Figure 10.
2X Basic write no delay
Figure 10 is a basic write transaction that transfers data at the 2X rate. There is no difference in the control
signals from AGP 1x mode - only more data is moved. The normal control signals determine when data is
valid.
Figure 11.
QuadWord writes back to back - no delays
Figure 11 illustrates multiple 8 byte write operations compared with the single transfer shown in Figure 10.
When the transactions are short, the arbiter is required to give grants on every clock or the AD bus will not
be totally utilized. In this example a new write is started on eachrising clock edge except clock 7, because
the arbiter deasserted
PCIGNT#
on clock 6. Since a new transaction is started on each CLK,
PCIIRDY#
is only deasserted on clock 7.
xxx
xxx
01x
xxx
xxx
xx
xxx
xxx
xxx
+2 +3 +4
W1 +1
+5 +6 +7
BE BE BE
BE BE
BE BE BE
PCICLK
PCIAD[31:0]
PCICBE#
AGPADSTBx
PCIIRDY#
PCITRDY#
PCIREQ#
PCIGNT#
AGPST[2:0]
1
2
3
4
5
6
7
8
9
01x
01x
01x
01x
xxx
xx
01x
01x
xxx
W6
+1
x
W5
+1
W7
+1
W3
+1
W4
+1
W8
+1
BE
BE
BE
BE
BE
BE
BE
BE
BE
BE
BE
BE
PCICLK
PCIAD[31:0
]
PCICBE#
AGPADSTBx
PCIIRDY#
PCITRDY#
PCIGNT#
AGPST[2:0]
1
2
3
4
5
6
7
8
9
相關PDF資料
PDF描述
RIVA128ZX 128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128 RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR
RIX-0142-H FILTER IEC EINGANG ULTRA KOMPAKT 1A
RIX-0342-H FILTER IEC EINGANG ULTRA KOMPAKT 3A
RIX-0642-H FILTER IEC EINGANG ULTRA KOMPAKT 6A
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