參數(shù)資料
型號(hào)： RIVA 128ZX
廠商： 意法半導(dǎo)體
英文描述： 128-Bit 3D Multimedia Accelerator(128位3D多媒體加速器)
中文描述： 128位3D多媒體加速器（128位三維多媒體加速器）
文件頁數(shù)： 7/85頁
文件大?。?/td> 608K
代理商： RIVA 128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
7/85
2.3
FRAMEBUFFER INTERFACE
2.4
VIDEO PORT
PCIGNT#
I
Grant. This signal indicates to the RIVA128ZX that access to the bus has been granted
and it can now become bus master.
When connected to AGP additional information is provided on
AGPST[2:0]
indicating that
the master is the recipient of previously requested read data (high or low priority), it is to
provide write data (high or low priority), for a previously enqueued write command or has
been given permission to start a bus transaction (AGP or PCI).
PCIINTA#
O
Interrupt request line. This open drain output is asserted and deasserted asynchronously
to
PCICLK
.
Signal
I/O
Description
FBD[127:0]
I/O
The 128-bit memory data bus.
FBD[31:0]
are also used to access up to 64KBytes of 8-bit ROM or Flash ROM, using
FBD[15:0]
as address ROMA[15:0],
FBD[31:24]
as ROMD[7:0],
FBD[17]
as ROMWE#
and
FBD[16]
as ROMOE#.
FBA[10:0]
O
Memory Address bus. Configuration strapping options are also decoded on these signals
during PCIRST# as described in Section 10, page 55.
FBRAS#
O
Memory Row Address Strobe for all memory devices.
FBCAS#
O
Memory Column Address Strobe for all memory devices.
FBCS[1:0]#
O
Memory Chip Select strobes. For SDRAM the
FBCS[1]
pin provides the memory’s inter-
nal bank select bit (BA/A11).
FBWE#
O
Memory Write Enable strobe for all memory devices.
FBDQM[15:0]
O
Memory Data/Output Enable strobes.
FBCLK0,
FBCLK1,
FBCLK2
O
Memory Clock signals. Separate clock signals
FBCLK0
and
FBCLK1
are provided for
each bank of memory for reduced clock skew and loading. Details of recommended mem-
ory clock layout are given in Section 6.4, page 37.
FBCLKFB
I
Framebuffer clock feedback.
FBCLK2
is fed back to
FBCLKFB
.
FBCKE
O
Framebuffer memory clock enable signal.
Signal
I/O
Description
MP_AD[7:0]
I/O
Media Port 8-bit multiplexed address and data bus or ITU-R-656 video data bus when in
656 mode.
40MHz Media Port system clock or pixel clock when in 656 mode.
Media Port data transfer acknowledgment signal.
Initiates Media Port transfers when active, terminates transfers when inactive.
Media Port control signal used by the slave to terminate transfers.
MPCLK
MPDTACK#
MPFRAME#
MPSTOP#
I
I
O
I
Signal
I/O
Description
相關(guān)PDF資料
PDF描述
RIVA128ZX 128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128 RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR
RIX-0142-H FILTER IEC EINGANG ULTRA KOMPAKT 1A
RIX-0342-H FILTER IEC EINGANG ULTRA KOMPAKT 3A
RIX-0642-H FILTER IEC EINGANG ULTRA KOMPAKT 6A
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