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參數(shù)資料
| 型號： | RIVA 128ZX |
| 廠商： | 意法半導體 |
| 英文描述： | 128-Bit 3D Multimedia Accelerator(128位3D多媒體加速器) |
| 中文描述： | 128位3D多媒體加速器（128位三維多媒體加速器） |
| 文件頁數(shù)： | 35/85頁 |
| 文件大?。?/td> | 608K |
| 代理商： | RIVA 128ZX |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
35/85
6.3
Read and write accesses to SDRAM/SGRAMare burst oriented. SDRAM/SGRAM commands supported
by the RIVA128ZX are shown in Table 9. Initialization of the memory devices is performed in the standard
SDRAM/SGRAM manner. Access sequences begin with an Active command followed by a Read or Write
command. The address bits registered coincident with the Read or Write command are used to select the
starting column location for the burst access. The RIVA128ZX always uses a burst length of one and can
launch a new read or write on every cycle.
SDRAM/SGRAM has a fully synchronous interface with all signals registered on the positive edge of
FB-
CLKx.
Multiple clock outputs allow reductions in signal loading and more accuracy in data sampling at
high frequency. The clock signals can be interspersed as shown in Figure 30, page 33 for optimal loading
with either 4 or 8MBytes. The I/O timings relative to
FBCLKx
are shown in Figure 32, page 37.
Table 8.
Truth table of supported SDRAM commands
SDRAM/SGRAM ACCESSES AND COMMANDS
NOTES
1
2
3
FBCKE
is high and DSF is low for all supported commands.
Activates or deactivates
FBD[63:0]
during writes (zero clock delay) and reads (two-clock delay).
For
FBA10
low,
FBCS[1]#
determines which bank is precharged; for
FBA10
high, all banks are precharged irrespective
of the state of
FBCS[1]#
.
Command
1
FBCS0# FBRAS# FBCAS# FBWE#
FBDQM
FBCS[1]#
,
FBA[10:0]
FBD[63:0] Notes
Command inhibit
(NOP)
H
x
x
x
x
x
x
No operation
(NOP)
L
H
H
H
x
x
x
Active
(select bank and
activate row)
L
L
H
H
x
FBCS[1]#
=bank
FBA[10:0]
=row
x
Read
(select bank and
column and start read
burst)
L
H
L
H
x
FBCS[1]#
=bank
FBA[10]
=0
FBA[7:0]
=col
x
Write
(select bank and
column and start write
burst)
L
H
L
L
x
FBCS[1]#
=bank
FBA[10]
=0
FBA[7:0]
=col
valid data
Precharge
(deactivate
row in bank or banks)
L
L
H
L
x
FBA[10]
=code
x
3
Load mode register
L
L
L
L
x
FBCS[1]#
,
FBA[10:0] =
opcode
Write enable/output
enable
-
-
-
-
L
-
active
2
Write inhibit/output
High-Z
-
-
-
-
H
-
high-Z
2
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