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參數(shù)資料
| 型號(hào)： | RIVA 128ZX |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128-Bit 3D Multimedia Accelerator(128位3D多媒體加速器) |
| 中文描述： | 128位3D多媒體加速器（128位三維多媒體加速器） |
| 文件頁(yè)數(shù)： | 45/85頁(yè) |
| 文件大?。?/td> | 608K |
| 代理商： | RIVA 128ZX |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
45/85
8
The RIVA128ZX Multimedia Accelerator introduc-
es a multi-function Video Port that has been de-
signed to exploit the bus mastering functionality of
the RIVA128ZX. The Video Port is compliant with
a simplified ITU-R-656 video format with control of
attached video devices performed through the
RIVA128ZX serial interface. Video Port support in-
cludes:
Windows 95 DirectMPEG API acceleration by
providing:
-
Bus mastered compressed data transfer to
attached DVD and MPEG-2 decoders
VIDEO PORT
-
Local interrupt and pixel stream handling
-
Hardware
pressed data, decompressed video pixel
data and decompressed audio streams
buffer
management
of com-
Supports popular video decoders including the
Philips SAA7111A, SAA7112, ITT 3225, and
Samsung KS0127. The Video Port initiates
transfers of video packets over the internal NV
bus to either on or off screen surfaces as de-
fined in the DirectDraw and DirectVideo APIs.
Supports filtered down-scaling or decimation
Allows additional devices to be added
Figure 45.
Connections to multiple video modules
8.1
Single 8-bit bus multiplexing among four trans-
fer types: video, VBI, host and compressed
data
Synchronous 40MHz address/data multiplexed
bus
Hardware-based round-robin scheduler with
predictable performance for all transfer types
VIDEO INTERFACE PORT FEATURES
Supports multiple video modules and one rib-
bon cable board on the same bus
ITU-R-656 Master Mode
Video Port
-
Simplified ITU-R-656 Video Format -- sup-
ports HSYNC, VSYNC, ODD FIELD and
EVEN FIELD
-
VBI data output from video decoder is cap-
tured as raw or sliced data
PCI/AGP
MPCLK
MPAD[7:0]
MPFRAME#
MPDTACK#
MPSTOP#
RIVA128ZX
Video
decoder
Media Port
Controller
(MPC)
S Video
VMI 1.4
ITU-R-656
DVD
Controller
TV tuner
SDA
SCL
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