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參數資料
| 型號： | RIVA 128ZX |
| 廠商： | 意法半導體 |
| 英文描述： | 128-Bit 3D Multimedia Accelerator(128位3D多媒體加速器) |
| 中文描述： | 128位3D多媒體加速器（128位三維多媒體加速器） |
| 文件頁數： | 5/85頁 |
| 文件大?。?/td> | 608K |
| 代理商： | RIVA 128ZX |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
5/85
2
PIN DESCRIPTIONS
2.1
ACCELERATED GRAPHICS PORT (AGP) INTERFACE
2.2
PCI 2.1 LOCAL BUS INTERFACE
Signal
I/O
Description
AGPST[2:0]
I
AGP status bus providing information from the arbiter to the RIVA128ZXon what it may
do.
AGPST[2:0]
only havemeaning to the RIVA128ZXwhen
PCIGNT#
is asserted. When
PCIGNT#
is de-asserted these signals have no meaningand must be ignored.
000
Indicates that previously requested low priority read or flush data is being
returned to the RIVA128ZX.
001
Indicates that previously requested high priority read data is being returned to
the RIVA128ZX.
010
Indicates that the RIVA128ZX is to provide low priority write data fora previous
enqueued write command.
011
Indicates that the RIVA128ZXis to provide high priority write data for a previous
enqueued write command.
100
Reserved
101
Reserved
110
Reserved
111
Indicates that the RIVA128ZX has been given permission to start a bus transac-
tion. The RIVA128ZX may enqueue AGP requests by asserting
AGPPIPE#
or
start a PCI transaction by asserting
PCIFRAME#
.
AGPST[2:0]
are always an
output from the Core Logic (AGP chipset) and an input to the RIVA128ZX.
AGPRBF#
O
Read BufferFull indicates when the RIVA128ZXis ready to accept previously requested
low priority read data or not. When
AGPRBF#
is asserted the arbiter is not allowed to
return (low priority) read data to the RIVA128ZX.This signal should be pulled up via a
4.7K
resistor (although it is supposed to be pulled up by the motherboard chipset).
AGPPIPE#
O
Pipelined Read is asserted byRIVA128ZX (when the current master) to indicate a full
width read address is to be enqueued by the target. The RIVA128ZXenqueues one
request each rising clock edge while
AGPPIPE#
is asserted. When
AGPPIPE#
is de-
asserted no new requests are enqueued across
PCIAD[31:0]
.
AGPPIPE#
is a sustained
tri-state signal from the RIVA128ZX and is an input to the target (the core logic).
AGPADSTB0
,
AGPADSTB1
I/O
Bus strobe signals providing timing for AGP2X data transfermode on
PCIAD[15:00]
and
PCIAD[31:16]
respectively. The agent that is supplying data drives these signals.
Signal
I/O
Description
PCICLK
I
PCI clock. This signal provides timing for all transactions on the PCI bus, exceptfor
PCIRST#
and
PCIINTA#
. All PCI signals are sampled on the rising edge of
PCICLK
and
all timing parameters are defined with respect to this edge.
PCIRST#
I
PCI reset. This signal is used to bring registers, sequencers and signals to a consistent
state. When
PCIRST#
is asserted all output signals are tristated.
PCIAD[31:0]
I/O
32-bit multiplexedaddress and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
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