參數(shù)資料
型號： RTL8309SB
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
中文描述： 單芯片9口10/100Mbps開關(guān)控制器
文件頁數(shù)： 108/115頁
文件大?。?/td> 866K
代理商： RTL8309SB
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
93
Track ID: JATR-1076-21 Rev. 1.4
Table 118. Digital Timing Characteristics
Condition
MAC Mode MII Timing
MTXC/MRXC, MRXC/PTXC clock cycle time
Parameter
SYM
I/O Min
Type Max
Units
100BaseT MTXC/MRXC,
MRXC/PTXC
10BaseT MTXC/MRXC,
MRXC/PTXC
MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV Output
Setup Time
MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV Output
Hold Time
MRXD[3:0]/PTXD[3:0],
MRXDV/PTXEN,
MCOL/PCOL Setup Time
MRXD/PTXD,
MRXDV/PTXEN,
MCOL/PCOL Hold Time
Parameter
T
cyc
I
40
±
50
ppm
400
±
50
ppm
24
ns
T
cyc
MTXC/MRXC, MRXC/PTXC clock cycle time
I
ns
T
os
Output Setup time from REFCLK rising edge to
MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV
O
22
26
ns
T
oh
Output Hold time from REFCLK rising edge to
MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV
O
14
16
18
ns
T
s
MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge setup time
I
4
ns
T
h
MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge hold time
I
2
ns
SYM
Condition
I/O Min
Type Max
Units
PHY Mode MII Timing
MTXC/MRXC, MRXC/PTXC, PHY2PTXC,
PHY2PRXC clock cycle time
MTXC/MRXC, MRXC/PTXC, PHY2PTXC,
PHY2PRXC clock cycle time
100BaseT MTXC/MRXC,
MRXC/PTXC,
10BaseT
MTXC/PRXC,
MRXC/PTXC,
MTXD/PRXD[3:0],
MTXEN/PRXDV,
MCOL/PCOL, Output
Setup Time
MTXD/PRXD[3:0],
MTXEN/PRXDV,
MCOL/PCOL, Output
Hold Time
MRXD/PTXD[3:0],
MRXDV/PTXEN, Setup
Time
MRXD/PTXD[3:0],
MRXDV/PTXEN, Hold
Time
T
cyc
O
40
±
50
ppm
400
±
50
ppm
ns
T
cyc
O
ns
T
os
Output Setup time from REFCLK rising edge to
MTXD[3:0]/PRXD[3:0], PHY2PRXD[3:0],
MTXEN/PRXDV, PHY2PRXDV
MCOL/PCOL, PHY2PCOL
Output Hold time from REFCLK rising edge to
MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV,
MCOL/PCOL
O
14
16
18
ns
T
oh
O
22
24
26
ns
T
s
MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge setup time
I
4
ns
T
h
MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge hold time
I
2
ns
PHY Mode SNI Timing
MTXC/PRXC, MRXC/PTXC clock cycle time
MTXC/MRXC,
MRXC/PTXC
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Output
Setup Time
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Output
Hold Time
MRXD/PTXD[0],
MRXDV/PTXEN Setup
Time
T
cyc
O
100
±
50
ppm
30
ns
T
os
Output Setup time from REFCLK rising edge to
MTXD[0]/PRXD[0], MTXEN/PRXDV,
MCOL/PCOL
O
28
32
ns
T
oh
Output Hold time from REFCLK rising edge to
MTXD[0]/PRXD[0], MTXEN/PRXDV,
MCOL/PCOL
O
68
70
72
ns
T
s
MTXD[0]/PRXD[0], MRXDV/PTXEN to
REFCLK rising edge setup time
I
4
ns
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