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參數(shù)資料
| 型號： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開關(guān)控制器 |
| 文件頁數(shù)： | 67/115頁 |
| 文件大小： | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
52
Track ID: JATR-1076-21 Rev. 1.4
7.3.10. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]
Table 84. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]
Mode Description
24[15:12] Port 2 VLAN
Index [3:0]
port 2’s ‘Port VLAN Membership’, which can be defined in one
of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 2 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
24[11~9] Reserved
This bytes are reserved for not used
24.[8:0] VLAN ID [C]
Membership Bit
[8:0]
this VLAN will be forwarded to ports specified in this field.
E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Reg.bit
Name
Default
0010
RW
In a port-based VLAN configuration, this register indexes
111
1
0000
0100
RW
This 9-bit field specifies which ports are members of VLAN C.
If a destination address look up fails, packets associated with
7.3.11. PHY 2 Register 25: VLAN Entry [C]
Table 85. PHY 2 Register 25: VLAN Entry [C]
Mode Description
RW
Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN C.
Reg.bit
25.[15:12] Reserved
25[11:0] VLAN ID [C]
Name
Default
1111
0000
0000
0010
7.4.
PHY 3 Registers
7.4.1.
PHY 3 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 40.
7.4.2.
PHY 3 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 41.
7.4.3.
PHY 3 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 42.
7.4.4.
PHY 3 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 42.
7.4.5.
PHY 3 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 43.
7.4.6.
PHY 3 Register 16~18: Switch MAC Address
The Switch MAC address is used as the source address in MAC pause control frames.
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