參數(shù)資料
型號: RTL8309SB
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
中文描述: 單芯片9口10/100Mbps開關(guān)控制器
文件頁數(shù): 66/115頁
文件大小: 866K
代理商: RTL8309SB
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
51
Track ID: JATR-1076-21 Rev. 1.4
7.3.4.
PHY 2 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 42.
7.3.5.
PHY 2 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 43.
7.3.6.
PHY 2 Register 16~17: IP Priority Mask [A]
Table 82. PHY 2 Register 16~17: IP Priority Mask [A]
Mode Description
RW
The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
IP Mask [A] [15:0]
RW
The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
Reg.bit
16
Name
IP Mask [A]
[31:16]
Default
0xFFFF
17
0xFFFF
7.3.7.
PHY 2 Register 18~19: IP Priority Mask [B]
Table 83. PHY 2 Register 18~19: IP Priority Mask [B]
Mode Description
RW
The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
IP Mask [B] [15:0]
RW
The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
Reg.bit
18
Name
IP Mask [B]
[31:16]
Default
0xFFFF
19
0xFFFF
7.3.8.
PHY 2 Register 22: Port 2 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 46.
Note: Reg 22.8 is pin Sel_PortPri strap option for port 2. Default value for 22.8 is 1.
7.3.9.
PHY 2 Register 23: Port 2 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 48.
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