參數(shù)資料
型號： RTL8309SB
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
中文描述： 單芯片9口10/100Mbps開關(guān)控制器
文件頁數(shù)： 77/115頁
文件大小： 866K
代理商： RTL8309SB
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
62
Track ID: JATR-1076-21 Rev. 1.4
7.8.7.
PHY 7 Register 17~20: Indirect Access Data
Table 101. PHY 7 Register 17~20: Indirect Access Data
Mode Description
RW
Bit 63~48 of indirect data.
Indirect Data [54] = If this bit is 1, indicates this entry is static
and will never be aged out. If this bit is 0, indicates this entry is
dynamically learned, aged, updated, and deleted.
Indirect Data [53:52] = 2-bit counter for internal aging.
Indirect Data [51:48] = The source port of this Source MAC
Address is learned.
RW
Bit 47~32 of indirect data.
Indirect Data [47:40] = Source MAC Address [39:32].
Indirect Data [39:32] = Source MAC Address [47:40].
RW
Bit 31~16 of indirect data.
Indirect Data [31:24] = Source MAC Address [23:16].
Indirect Data [23:16] = Source MAC Address [31:24].
RW
Bit 15~0 of indirect data.
Indirect Data [15:8] = Source MAC Address [7:0].
Indirect Data [7:0] = Source MAC Address [15:8].
Bits 1~0 and Bits 15~8 of this register also determine the
address of data in the lookup table.
In a write cycle: Bits 1~0 and Bits 15~8 indirectly map to an
entry in the lookup table. The written data should be filled in
Indirect Data [63:0]
In a read cycle: Bits 1~0 and Bits 15~8 indirectly map to an
entry in the lookup table. The read back data will be shown in
Indirect Data [63:0].
Reg.bit
17
Name
Indirect Data
[63:48]
Default
0x00
18
Indirect Data
[47:32]
0x00
19
Indirect Data
[31:16]
0x00
20
Indirect Data
[15:0]
0x00
7.8.8.
PHY 7 Register 22: Port 7 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 46.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 7. Default value for 22.8 is 1.
7.8.9.
PHY 7 Register 23: Port 7 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 48.
7.8.10. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]
Table 102. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]
Mode Description
24[15:12] Port 7 VLAN index
[3:0]
port 7’s ‘Port VLAN Membership’, which can be defined in one
of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 7 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
24.[11~9] Reserved
Reg.bit
Name
Default
0111
RW
In a port-based VLAN configuration, this register indexes
111
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