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參數(shù)資料
| 型號(hào)： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開(kāi)關(guān)控制器 |
| 文件頁(yè)數(shù)： | 88/115頁(yè) |
| 文件大?。?/td> | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
73
Track ID: JATR-1076-21 Rev. 1.4
MII PHY Mode/SNI PHY Mode
In routing applications, the RTL8309SB cooperates with a routing engine to communicate with the WAN (Wide Area
Network) through MII/SNI.
In MII PHY mode, pulling MII_SPD_STA up results in the MII port operating at 100Mbps with MTXC, and MRXC running
at 25MHz. Pulling MII_SPD_STA down results in the MII port operating at 10Mbps with MTXC, and MRXC running at
2.5MHz.
In SNI PHY mode, MII_SPD_STA has no effect and should be pulled down. SNI mode operates at 10Mbps only, with MTXC
and MRXC running at 10MHz. In SNI mode, the RTL8309SB does not loop back a RXDV signal as a response to TXEN and
does not support the heartbeat function (asserting COL signal for each complete TXEN signal). This interface is a bit-wide
data interface used with some controllers to function as a network layer protocol in half duplex operation.
MII MAC Mode
In HomePNA or other PHY applications, the RTL8309SB provides an MII interface to the underlying HomePNA or other
physical devices so as to communicate with other types of LAN media. In such applications, MII_MODE[1:0] should be
pulled high or be floated upon reset.
In HomePNA applications, MII_DUP_STA must be pulled down since HomePNA is half-duplex only. The link speed of the
RTL8309SB is determined by RXC and TXC from the PHY of the HomePNA (running at 1Mbps). Thus, the MII_SPD_STA
has no effect and should be pulled down for compatibility with HomePNA’s PHY. The link state of HomePNA is unstable (a
characteristic of the HomePNA 1.0 standard) such that MII_LNK_STA# must be pulled down instead of being wired to the
LINK LED pin of the HomePNA.
Because the HomePNA PHY physical layer is half duplex and can only detect a collision event during the AID header interval
(the time when transmitting the Ethernet preamble), the backpressure flow control algorithm is not suitable for a HomePNA
network and MII_FCTRL_STA should be pulled down.
For other PHY applications, the strap status set by MII_SPD_STA, MII_DUP_STA, and MII_FCTRL_STA depends on the
particular application.
MII Port PHY Register
The external MAC automatically polls and accesses the internal PHY registers in the RTL8309SB when the MII port is
operated in MII PHY mode with auto negotiation enabled. For the auto negotiation process in the CPU to function properly,
the RTL8309SB provides PHY register 0, 1, and 4, to virtually provide the MII port’s PHY status to the external MAC.
Because the MII port of the RTL8309SB does not have a true PHY in it, it does not process the auto negotiation. The contents
of PHY registers 4 and 5 should be the same for both terminals of the MII bus when operating on the same link status. Thus,
the RTL8309SB does not provide PHY register 5; it only emulates it. If the CPU polls PHY register 5, the RTL8309SB returns
the contents of PHY register 4 since it cannot execute the auto negotiation process. If the CPU polls PHY register 4, the
RTL8309SB returns the contents of PHY register 4.
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