RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.4
8.
Functional Description
8.1.
Physical Layer Transceiver Functional Overview
8.1.1.
Auto Negotiation for UTP
The RTL8309SB obtains the states of duplex, speed, and flow control ability for each port in UTP mode through the auto-
negotiation mechanism defined in the IEEE 802.3u specifications. During auto-negotiation, each port advertises its ability to its
link partner and compares its ability with advertisements received from its link partner. By default, the RTL8309SB advertises
full capabilities (100Full, 100Half, 10Full, 10Half) together with flow control ability.
If the link partner to the RTL8309SB is forced to bypass auto negotiation, or auto negotiation is not supported, the link status
of the RTL8309SB is determined by observing the signal at the receiver.
8.1.2.
100Base-Tx Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion,
and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream
Cipher function to flatten the power spectrum energy such that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit stream is driven onto the
network media in the form of MLT-3 signaling. The MLT-3 multi-level signaling technology moves the power spectrum
energy from high frequency to low frequency, which also benefits EMI emission.
8.1.3.
100Base-Tx Receive Function
The 100Base-TX receive mechanism includes an adaptive equalizer, DC restoration, MLT3 to NRZI conversion, data and
clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding, and serial to parallel conversion. The process starts
with the adaptive equalizer and DC restoration circuits to compensate for the distortion in the MLT-3 signal. This variable
equalizer makes an estimate by comparing the received signal strength against some known cable characteristic, then tunes
itself for optimization. This on-going process allows the RTL8309SB to adjust itself to environmental changes such as
temperature variations. The equalized data then goes through a DC restoration circuit to compensate for the effects of base line
wander in order to improve the dynamic range.
After restoration, the MLT-3 to NRZI, NRZI to NRZ converters then convert the analog signal to a digital bit-stream. The
clock recovery circuit extracts the 125MHz clock from the edges of the NRI signal. A De-scrambler, 5B/4B decoder and serial-
to-parallel conversion circuits follow. Finally, the converted parallel data is fed into the MAC.