參數(shù)資料
型號(hào): RTL8309SB
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
中文描述: 單芯片9口10/100Mbps開關(guān)控制器
文件頁(yè)數(shù): 61/115頁(yè)
文件大?。?/td> 866K
代理商: RTL8309SB
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
46
Track ID: JATR-1076-21 Rev. 1.4
7.1.8.
PHY 0 Register 18: Global Control 2
Table 72. PHY 0 Register 18: Global Control 2
Mode Description
RW
1: If differential service priority is enabled, this bit specifies
differential service code point [A] is high priority
0: If differential service priority is enabled, this bit specifies
differential services code point [A] is low priority
RW
Used to specify the high priority differential service code
point A. For example, if these bits are set to 111111, incoming
packets with a TOS field equal to 111111 will be considered
high priority packets.
RW
1: If differential service priority is enabled, this bit specifies
differential services code point [B] is high priority
0: If differential service priority is enabled, this bit specifies
differential services code point [B] is low priority
RW
Used to specify a high priority differential service code point B.
For example, if these bits are set to 000000, incoming packets
with a TOS field equal to 000000 will be considered high
priority packets.
Reg.bit
18.15
Name
Enable differential
service code point
[A]
Default
0
18.14
18.[13:8] Differential service
code point [A]
Reserved
1
111111
18.7
Enable differential
service code point
[B]
0
18.6
18.[5:0] Differential service
code point [B]
Reserved
1
111111
7.1.9.
PHY 0 Register 19: Global Control 3
Table 73. PHY 0 Register 19: Global Control 3
Mode Description
RW
1: Enable drop packet after SRAM full for 48 pass 1
0: Disable drop packet after SRAM full for 48 pass 1. This will
result in SRAM run out
RW
1: 90ppm TX IPG (InterPacketGap) compensation
0: 65ppm TX IPG (InterPacketGap) compensation
RW
1: Disable loop detection function
0: Enable loop detection function
RW
1: Lookup table is accessible via indirect access registers
0: Lookup table is not accessible
Reg.bit
19.15
Name
Enable drop for 48
pass 1
Default
1
19.14
19.13
Reserved
TX IPG
compensation
Disable loop
detection
Lookup table
accessible enable
Reserved
1
1
19.12
1
19.11
0
19.10
19.[9:0] Reserved
1
11 1100 0001
7.1.10. PHY 0 Register 22: Port 0 Control 0
Table 74. PHY 0 Register 22: Port 0 Control 0
Mode Description
RW
Reserved.
RW
1: Perform ‘local loopback’, i.e. loop MAC’s RX back to TX
0: Normal operation
RW
1: The switch will replace a NULL VID with a port VID (12
bits)
0: No replacement for a NULL VID
Reg.bit
22.[15:14] Reserved
22.13
Name
Default
11
0
Local loopback
22.12
Null VID
replacement
0
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