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參數(shù)資料
| 型號(hào)： | SC1100UFH-300 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Geode⑩ Information Appliance On a Chip |
| 中文描述： | Geode⑩信息家電在一個(gè)芯片 |
| 文件頁數(shù)： | 128/348頁 |
| 文件大?。?/td> | 2063K |
| 代理商： | SC1100UFH-300 |
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128
Revision 1.1
G
Core Logic Module
(Continued)
In
block
transfer mode, the DMA controller executes all of
its transfers consecutively without releasing the PCI bus.
In
demand
transfer mode, DMA transfer cycles continue to
occur as long as DRQ is high or terminal count is not
reached. In this mode, the DMA controller continues to exe-
cute transfer cycles until the I/O device drops DRQ to indi-
cate its inability to continue providing data. For this case,
the PCI bus is held by the Core Logic module until a break
in the transfers occurs.
In
cascade
mode, the channel is connected to another
DMA controller or to an ISA bus master, rather than to an
I/O device. In the Core Logic module, one of the 8237 con-
trollers is designated as the master and the other as the
slave. The HOLD output of the slave is tied to the DRQ0
input of the master (Channel 4), and the master’s DACK0#
output is tied to the slave’s HLDA input.
In each of these modes, the DMA controller can be pro-
grammed for
read
,
write,
or
verify
transfers.
Both DMA controllers are reset at power-on reset (POR) to
fixed
priority. Since master Channel 0 is actually connected
to the slave DMA controller, the slave’s four DMA channels
have the highest priority, with Channel 0 as highest and
Channel 3 as the lowest. Immediately following slave
Channel 3, master Channel 1 (Channel 5) is the next high-
est, followed by Channels 6 and 7.
DMA Controller Registers
The DMA controller can be programmed with standard I/O
cycles to the standard register space for DMA. The I/O
addresses for the DMA controller registers are listed Table
5-43 on page 265.
When writing to a channel's address or WORD Count reg-
ister, the data is written into both the base register and the
current register simultaneously. When reading a channel
address or WORD Count register, only the current address
or WORD Count can be read. The base address and base
WORD Count are not accessible for reading.
DMA Transfer Types
Each of the seven DMA channels may be programmed to
perform one of three types of transfers:
read, write, or ver-
ify
. The transfer type selected defines the method used to
transfer a byte or WORD during one DMA bus cycle.
For
read
transfer types, the Core Logic module reads data
from memory and writes it to the I/O device associated with
the DMA channel.
For
write
transfer types, the Core Logic module reads data
from the I/O device associated with the DMA channel and
writes it to the memory.
The
verify
transfer type causes the Core Logic module to
execute DMA transfer bus cycles, including generation of
memory addresses, but neither the READ nor WRITE com-
mand lines are activated. This transfer type was used by
DMA Channel 0 to implement DRAM refresh in the original
IBM PC and XT.
DMA Priority
The DMA controller may be programmed for two types of
priority schemes:
fixed
and
rotate
(I/O Ports 008h[4] and
0D0h[4] - see Table 5-43 on page 265).
In
fixed
priority, the channels are fixed in priority order
based on the descending values of their numbers. Thus,
Channel 0 has the highest priority. In
rotate
priority, the last
channel to get service becomes the lowest-priority channel
with the priority of the others rotating accordingly. This pre-
vents a channel from dominating the system.
The address and WORD Count registers for each channel
are 16-bit registers. The value on the data bus is written
into the upper byte or lower byte, depending on the state of
the internal addressing byte pointer. This pointer can be
cleared by the Clear Byte Pointer command. After this com-
mand, the first read/write to an address or WORD Count
register reads or writes to the low byte of the 16-bit register
and the byte pointer points to the high byte. The next
read/write to an address or WORD Count register reads or
writes to the high byte of the 16-bit register and the byte
pointer points back to the low byte.
When programming the 16-bit channels (Channels 5, 6,
and 7), the address which is written to the base address
register must be the real address divided by two. Also, the
base WORD Count for the 16-bit channels is the number of
16-bit WORDs to be transferred, not the number of bytes
as is the case for the 8-bit channels.
The DMA controller allows the user to program the active
level (low or high) of the DRQ and DACK# signals. Since
the two controllers are cascaded together internally on the
chip, these signals should always be programmed with the
DRQ signal active high and the DACK# signal active low.
DMA Shadow Registers
The Core Logic module contains a shadow register located
at F0 Index B8h (Table 5-29 on page 166) for reading the
configuration of the DMA controllers. This read only regis-
ter can sequence to read through all of the DMA registers.
DMA Addressing Capability
DMA transfers occur over the entire 32-bit address range of
the PCI bus. This is accomplished by using the DMA con-
troller’s 16-bit memory address registers in conjunction
with an 8-bit DMA Low Page register and an 8-bit DMA
High Page register. These registers, associated with each
channel, provide the 32-bit memory address capability. A
write to the Low Page register clears the High Page regis-
ter, for backward compatibility with the PC/AT standard.
The starting address for the DMA transfer must be pro-
grammed into the DMA controller registers and the chan-
nel’s respective Low and High Page registers prior to
beginning the DMA transfer.
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