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26
Revision 1.1
G
Signal Definitions
(Continued)
AE22
SYNC
O
O
2/5
V
IO
---
CLKSEL3
I
(PD
100
)
IN
AB
Strap
AE23
GPIO12
I/O
(PU
22.5
)
IN
AB
,
O
2/8
V
IO
PMR[19] = 0 and
PMR[27] = 0 and
FPCI_MON = 0
AB2C
I/O
(PU
22.5
)
IN
AB
,
OD
8
PMR[19] = 1 and
PMR[27] = 0 and
FPCI_MON = 0
F_AD3
O
(PU
22.5
)
O
2/8
PMR[27] = 1 or
FPCI_MON = 1
(overrides PMR[19])
AE24
NC
---
---
---
---
AE25
V
SS
GND
---
---
---
AE26
V
IO
PWR
---
---
---
AF1
V
SS
GND
---
---
---
AF2
V
IO
PWR
---
---
---
AF3
IDE_DATA11
I/O
IN
TS1
,
TS
1/4
V
IO
---
AF4
IDE_DATA10
I/O
IN
TS1
,
TS
1/4
V
IO
---
AF5
IDE_DATA9
I/O
IN
TS1
,
TS
1/4
V
IO
---
AF6
AV
CCUSB
PWR
---
---
---
AF7
DPOS_PORT2
I/O
IN
USB
,
O
USB
AV
C-
CUSB
---
AF8
DNEG_PORT2
I/O
IN
USB
,
O
USB
AV
C-
CUSB
---
AF9
AV
SSPLL
GND
---
---
---
AF10
X27I
I
WIRE
V
IO
---
AF11
GPIO7
I/O
(PU
22.5
)
IN
TS
,
O
1/4
V
IO
PMR[17] = 0 and
PMR[8] = 0 and
PMR[27] = 0 and
FPCI_MON = 0
RTS#
O
O
1/4
PMR[17] = 1 and
PMR[8] = 0 and
PMR[27] = 0 and
FPCI_MON = 0
IDE_DACK1#
O
(PU
22.5
)
O
1/4
PMR[17] = 0 and
PMR[8] = 1 and
PMR[27] = 0 and
FPCI_MON = 0
F_C/BE3#
O
O
1/4
PMR[27] = 1 or
FPCI_MON = 1
(overrides PMR[17]
and PMR[8])
AF12
GPIO10
I/O
(PU
22.5
)
IN
TS
,
O
1/4
V
IO
PMR[18] = 0 and
PMR[8] = 0 and
PMR[27] = 0 and
FPCI_MON = 0
DSR#
I
IN
TS
PMR[18] = 1 and
PMR[8] = 0 and
PMR[27] = 0 and
FPCI_MON = 0
IDE_IORDY1
I
(PU
22.5
)
IN
TS1
PMR[18] = 0 and
PMR[8] = 1 and
PMR[27] = 0 and
FPCI_MON = 0
F_FRAME#
O
O
1/4
PMR[27] = 1 or
FPCI_MON = 1
(overrides PMR[18]
and PMR[8])
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
AF13
V
CORE
PWR
---
---
---
AF14
V
CORE
PWR
---
---
---
AF15
PWRBTN#
I
(PU
100)
IN
BTN
V
SB
---
AF16
V
SB
PWR
---
---
---
AF17
GPWIO2
I/O
(PU
100
)
IN
BTN
,
TS
2/14
V
SB
---
AF18
2,3
PWRCNT2
O
OD
14
V
SB
---
AF19
GPIO11
I/O
(PU
22.5
)
IN
TS
,
O
8/8
V
IO
PMR[18] = 0 and
PMR[8] = 0
RI#
I
(PU
22.5
)
IN
TS
V
SB
/V
IO
PMR[18] = 1 and
PMR[8] = 0
(Note: Power rail
controlled by SW)
IRQ15
I
(PU
22.5
)
IN
TS
V
IO
PMR[18] = 0 and
PMR[8] = 1
AF20
TDI
I
(PU
22.5
)
IN
PCI
V
IO
---
AF21
TMS
I
(PU
22.5
)
IN
PCI
V
IO
---
AF22
SDATA_IN
I
IN
T
V
IO
PMR[27] = 0 and
FPCI_MON = 0
F_GNT0#
O
O
2/5
PMR[27] = 1 or
FPCI_MON = 1
AF23
AC97_RST#
O
O
2/5
V
IO
PMR[27] = 0 and
FPCI_MON = 0
F_STOP#
O
O
2/5
PMR[27] = 1 or
FPCI_MON = 1
AF24
NC
---
---
---
---
AF25
V
IO
PWR
---
---
---
AF26
V
SS
GND
---
---
---
1.
For Buffer Type definitions, refer to Table 7-7 "Buffer
Types" on page 286.
Is back-drive protected (MD[63:0], DOS_PORT1,
DNEG_PORT1, DOS_PORT2, DNEG_PORT2,
DOS_PORT3, DNEG_PORT3, ONCTL#, and
PWRCNT[2:1]).
Is 5V tolerant (ONCTL# and PWRCNT[2:1])
2.
3.
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
Table 2-2. Ball Assignment - Sorted by Ball Number (Continued)