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256
Revision 1.1
G
Core Logic Module
(Continued)
Offset 14h-17h
HcInterruptDisable Register (R/W)
Reset Value = 00000000h
31
MasterInterruptEnable.
Global interrupt disable. A write of 1 disables all interrupts.
30
OwnershipChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Ownership Change.
29:7
Reserved.
Read/Write 0s.
6
RootHubStatusChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Root Hub Status Change.
5
FrameNumberOverflowEnable.
0: Ignore.
1: Disable interrupt generation due to Frame Number Overflow.
4
UnrecoverableErrorEnable.
This event is not implemented. All writes to this bit will be ignored.
3
ResumeDetectedEnable.
0: Ignore.
1: Disable interrupt generation due to Resume Detected.
2
StartOfFrameEnable.
0: Ignore.
1: Disable interrupt generation due to Start of Frame.
1
WritebackDoneHeadEnable.
0: Ignore.
1: Disable interrupt generation due to Writeback Done Head.
0
SchedulingOverrunEnable.
0: Ignore.
1: Disable interrupt generation due to Scheduling Overrun.
Note:
Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 to a bit leaves the bit unchanged.
Offset 18h-1Bh
HcHCCA Register (R/W)
Reset Value = 00000000h
31:8
HCCA.
Pointer to HCCA base address.
7:0
Reserved.
Read/Write 0s.
Offset 1Ch-1Ch
HcPeriodCurrentED Register (R/W)
Reset Value = 00000000h
31:4
PeriodCurrentED.
Pointer to the current Periodic List ED.
3:0
Reserved.
Read/Write 0s.
Offset 20h-23h
HcControlHeadED Register (R/W)
Reset Value = 00000000h
31:4
ControlHeadED.
Pointer to the Control List Head ED.
3:0
Reserved.
Read/Write 0s.
Offset 24h-27h
HcControlCurrentED Register (R/W)
Reset Value = 00000000h
31:4
ControlCurrentED.
Pointer to the current Control List ED.
3:0
Reserved.
Read/Write 0s.
Offset 28h-2Bh
HcBulkHeadED Register (R/W)
Reset Value = 00000000h
31:4
BulkHeadED.
Pointer to the Bulk List Head ED.
3:0
Reserved.
Read/Write 0s.
Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description