3-10
SC140 DSP Core Reference Manual
Control Registers
3.1.2.1 Clearing EMR Bits
The ILIN, ILST, DOVF, and NMID bits can only be set by the hardware. These events should be regarded
as asynchronous to the program flow given the complex relationship between the events that set these bits
and the program flow.
To ensure that no information about new events is lost, the EMR bits should be cleared with great care. An
EMR bit is cleared by writing back 1 to it using the BMCLR instruction typically inside an exception
service routine. Example 3-1 illustrates the use of the BMCLR instruction in the interrupt service routine
of an overflow exception, which is activated when DOVF is set.
Example 3-1. Clearing an EMR Bit
BMCLR
#$fffb,EMR.L
This instruction writes back a zero to every bit in EMR.L except for DOVF, which is written with the same
value it contained when it was read. Because DOVF was set to begin with, it is now cleared. Other bits set
in EMR.L are not affected. Due to this special behavior, the EMR should not be stored to the stack during
a context switch. This ensures that no bits are cleared unintentionally when the EMR is restored.
3.2 PLL and Clock Registers
The SC140 core provides a programming interface to an on-chip phase-locked loop (PLL). The core has
two registers that control settings for the PLL as well as clocks. This section describes these control
registers.
A number of restrictions apply when making write operations to these registers. For further details, refer to
Section 6.4, “Instruction Set Restrictions,”
on page 6-17.
3.2.1 PLL Control Register 0 (PCTL0)
PCTL0 is a 32-bit read/write register used to direct the operation of a PLL. The register samples core
interface signals during hardware reset. These reset values are derivative-dependent. In certain PLL
implementations, the reset value of some or all of the bits may be determined by external pins. In all
implementations, the bits are read/write, and can be modified by program instructions.
3.2.2 Clock Control Register 1 (PCTL1)
PCTL1 is a 32-bit read/write register used to store the control bits of the on-core clock module as well as
the value of the post divider factor (low power divider). The register samples the core interface during
hardware reset. The use of bits 31–17 is derivative-dependent. Bits 15–0 are reserved for Starcore use.
These bits are read/write and sample a core interface input signal at reset. The value of each bit is available
on a core interface output signal. Four of these bits are defined in Figure 3-3 and Table 3-6.