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參數(shù)資料
| 型號： | SC140 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-Performance Fix-Point DSP Core(高性能定點型數(shù)字信號處理器內核) |
| 中文描述： | 高性能固定點DSP內核（高性能定點型數(shù)字信號處理器內核） |
| 文件頁數(shù)： | 70/672頁 |
| 文件大?。?/td> | 7960K |
| 代理商： | SC140 |
2-36
SC140 DSP Core Reference Manual
Core Architecture
2.3.2.2.1 Shadow Stack Pointer Registers
Both stack pointers have shadow registers which contain a decremented value of the stack pointers. When
the shadow register is not valid, the POP instruction is executed in two cycles. The first cycle is used to
decrement the stack pointer. When the shadow register is valid, the POP instruction is executed in only one
cycle.
When an SP is written by the AAU register transfer (TFRA), its shadow register automatically becomes
invalid. When a PUSH/POP instruction is executed, the shadow register of the active SP becomes valid. As
a result, during consecutive POPs, even in the worst case, only the first POP requires an additional cycle.
2.3.2.2.2 Initializing ESP
ESP should be initialized using the AAU register transfer (TFRA) instruction. This guarantees a valid ESP
value even if execution of this instruction is interrupted by an exception. The TFRA instruction is
considered an address arithmetic operation. The ESP is updated at the address generation pipeline stage,
avoiding pipeline conflicts.
2.3.2.3 Offset Registers (N0
–
N3)
The four 32-bit read/write offset registers N0–N3 can contain offset values used to increment or decrement
address registers in address register update calculations. These registers can also be used for 32-bit general
purpose storage. For example, the contents of an offset register can specify the offset into a table or the
base of the table for indexed addressing, or can be used to step through a table at a specified rate (for
example, five locations per step for waveform generation). Each address register can be used with each
offset register. For example, R0 can be used with N0, N1, N2, or N3 for offset address calculations. The
signed value in an offset register is pre-shifted to the left by 0, 1, 2, or 3 bits to align to the access width.
2.3.2.4 Base Address Registers (B0
–
B7)
The eight 32-bit read/write base address registers B0–B7 are used in modulo calculations. Each B register
is associated with an R register (B0 with R0, and so on). When activating the modulo addressing mode, the
B register contains the lower boundary value of the modulo buffer. The upper boundary of the modulo
buffer is calculated by B+M-1, where M is the modifier register associated with the R register by MCTL.
When not used for modulo addressing, these registers can be used as high bank address registers
(R8–R15). Both Rn and Bn
-8
share the same physical register. For example, if R0 is not programmed for
modulo addressing, the base address register B0 can serve as an additional address register R8.
2.3.2.5 Modifier Registers (M0
–
M3)
The four 32-bit read/write modifier registers M0–M3 can contain the value of the modulus modifier. These
registers can also be used for general-purpose storage. When activating the modulo arithmetic, the contents
of Mj specify the modulus. Each low address register can be used with each modifier register as
programmed in the MCTL register.
2.3.2.6 Modifier Control Register (MCTL)
The MCTL register is a 32-bit read/write register. This control register is used to program the address
mode (AM) for each of the eight low address registers (R0–R7). The addressing mode of the high address
register file (R8–R15) cannot be programmed and functions in linear addressing mode only. The format of
MCTL is shown in Figure 2-14.
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