Exception Processing
SC140 DSP Core Reference Manual
5-35
5.5.4.2 TRAP
On a TRAP instruction, the core enters the exception state. Both the PC and SR values are pushed onto the
exception stack. The IPL is set to its maximum value and the exception state is entered. This exception is
precise
. It occurs immediately after the execution set that contains the TRAP instruction.
5.5.4.3 Debug Exception
A debug exception can only be initiated by the EOnCE. Refer to
Chapter 4, “Emulation and Debug
(EOnCE),”
for further details.