
SC140 DSP Core Reference Manual
6-1
Chapter 6
Instruction Set Overview
The SC140 architecture can be viewed as several functional units operating in parallel:
Four arithmetic logic units (ALUs)
Two address arithmetic units (AAUs)
One bit mask unit (BMU)
One program controller (PSEQ)
Each instruction activates one functional unit. Several instructions can be grouped together for parallel
execution.
The instruction set has been designed to enable efficient parallel execution of DSP algorithms and control
code, using high-level language compilers, achieving maximum speed and minimum power consumption.
This extensive range of instruction capabilities also provides a very powerful assembly language for DSP
algorithms and general-purpose computing. Certain restrictions apply regarding the ability to group
instructions that activate the various units, because of their use of shared resources.
This chapter contains information on instruction grouping, timing, and restrictions. Each instruction has a
separate description in
Appendix A, “SC140 DSP Core Instruction Set.”
6.1 Instruction Types
The instruction set is divided into the following functional groups:
DALU arithmetic instructions, as described in
Section 2.2.1, “DALU Architecture,”
on page 2-6
Logical & bit-field instructions, as described in
Section 2.2.1.3, “Bit-Field Unit (BFU),”
on page
2-12
AGU arithmetic instructions, as described in
Section 2.3.1, “AGU Architecture,”
on page 2-31
Bit mask instructions, as described in
Section 2.3.6, “Bit Mask Instructions,”
on page 2-48
Move instructions, as described in
Section 2.3.7, “Move Instructions,”
on page 2-50
Change-of-flow instructions, as described in
Section 5.1.4, “Change-of-Flow Instructions,”
on page
5-7
Program control instructions, as described in
Section 5.1.5, “Program Control Instructions,”
on page
5-10
Loop instructions, as described in
Section 5.2.6, “Loop Instructions,”
on page 5-16
Stack support instructions, as described in
Section 5.3, “Stack Support,”
on page 5-19