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SC140 DSP Core Reference Manual
Instruction Set Overview
The restriction identification numbers that appear in the sections that follow are the actual identification
numbers given by the assembler at assembly time. The message numbers are in sequence within each
section. Missing numbers reflect messages that are no longer relevant, or were moved to other appropriate
sections.
6.4.1 General Grouping Restrictions
These general restrictions apply to both serial and prefix grouping types:
Restriction G.G.1
— Up to six instructions can be grouped.
Restriction G.G.2
— Total instruction word count in a set cannot exceed eight, including prefix
words. An example of a restricted sequence is:
JMPD R5 ADR D0,D12 ADR D1,D2 ADR D2,D3 ADR D5,D6 MOVE.L #$12345678,R0
In this case, there are six instructions, two prefix words, and two extra words for the MOVE.
Restriction G.G.3
— Instructions in a set can activate only the number of execution units available
in the SC140. Therefore, the maximum number of operations in a set is:
— Four DALU operations
— Two AGU operations, including:
– All moves (including move immediate)
– All AGU arithmetic instructions
– All bit mask operations (BMSET/CLR/CHG/TSTS/TSTC/TSET)
– All control operations (change-of-flow, low-power modes, and so on)
— One bit mask operation (BMSET/CLR/CHG/TSTS/TSTC/TSET) counted as an AGU operation
and cannot be grouped with another bit mask operation. An example of a restricted sequence is:
BMTSTS #$eb22,D5.H & MOVE.W R2,(R0)+ & MOVE.W R2,(R5)
Restriction G.G.4
— A register cannot be the destination of more than one instruction per subgroup
such that:
— Jumps (and any changes of flow) are PC updates. Multiple change-of-flow instructions are not
allowed.
— Multiple updates of the T-bit are not allowed. Instructions such as TST and CMPA or DECEQ
and BMTSET (for example) cannot be grouped.
— Dual updates of address registers are not allowed (for example, the combination
MOVE.W (R0)+, D1 and MOVE.W D2, (R0)+ is not allowed).
— Dual updates of the stack pointer (implicit or explicit) are not allowed (for example, POP cannot
be grouped with RTS).
— The following cases are exceptions to Restriction G.G.4:
– The pairs listed below update SP implicitly and can be grouped together. EEEEE and eeeee
are encodings for two groups of registers, odd and even. For these pairs, dedicated logic
ensures that SP will be updated correctly.
PUSH EEEEE
PUSHN EEEEE
POP EEEEE
POPN EEEEE
PUSH eeeee
PUSHN eeeee
POP eeeee
POPN eeeee
– Multiple updates of the C-bit in SR are allowed, but only the last update in the set is
performed. For example, two ADD or ASL instructions are allowed.