參數(shù)資料
型號(hào)： SN54ABT8373
廠商： Texas Instruments, Inc.
英文描述： Scan Test Devices With Octal D-Type Latches(掃描測(cè)試裝置(帶八D鎖存器))
中文描述： 掃描測(cè)試設(shè)備與八路D類鎖存器（掃描測(cè)試裝置（帶八?鎖存器））
文件頁(yè)數(shù)： 11/19頁(yè)
文件大小： 391K
代理商： SN54ABT8373
SN54ABT8373, SN74ABT8373
SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SCBS487 – JULY 1994
3–11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control-Register Opcodes
BINARY CODE
BIT 2
→
BIT 0
MSB
→
LSB
X00
X01
X10
011
111
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
Pseudo-random pattern generation/16-bit mode (PRPG)
Parallel-signature analysis/16-bit mode (PSA)
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)
It should be noted, in general, that while the control input BSCs (bits 17–16) are not included in the sample,
toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSC (bit 16 of the BSR) does control the drive
state (active or high impedance) of the device output pins.
PSA input masking
Bits 10–3 of the BCR specify device input pins to be masked from PSA operations. Bit 10 selects masking for
device input pin D8. Bit 3 selects masking for device input pin D1. Bits intermediate to 10 and 3 mask
corresponding device input pins in order from most significant to least significant, as indicated in Table 3. When
the mask bit that corresponds to a particular device input has a logic 1 value, the device input pin is masked
from any PSA operation, meaning that the state of the device input pin is ignored and has no effect on the
generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not
masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the device input pins is captured in the shift-register elements of the input BSCs on each rising
edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of
the normal on-chip logic. Data in the shift-register elements of the output BSCs is toggled on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK.
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相關(guān)PDF資料
PDF描述
SN74ABT8373 Scan Test Devices With Octal D-Type Latches(掃描測(cè)試裝置(帶八D鎖存器))
SN54ABT8374 Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測(cè)試裝置(帶八D邊沿觸發(fā)器))
SN74ABT8374 Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測(cè)試裝置(帶八D邊沿觸發(fā)器))
SN54ABT845 Octal Bus Interface D-Type Latches With 3-State Outputs(八總線接口D鎖存器(三態(tài)輸出))
SN74ABT845 Octal Bus Interface D-Type Latches With 3-State Outputs(八總線接口D觸發(fā)器(三態(tài)輸出))
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