參數(shù)資料
型號(hào): SN54ABT8373
廠商: Texas Instruments, Inc.
英文描述: Scan Test Devices With Octal D-Type Latches(掃描測(cè)試裝置(帶八D鎖存器))
中文描述: 掃描測(cè)試設(shè)備與八路D類鎖存器(掃描測(cè)試裝置(帶八?鎖存器))
文件頁(yè)數(shù): 3/19頁(yè)
文件大?。?/td> 391K
代理商: SN54ABT8373
SN54ABT8373, SN74ABT8373
SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SCBS487 – JULY 1994
3–3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
DESCRIPTION
GND
Ground
LE
Normal-function latch-enable input. See function table for normal-mode logic.
OE
Normal-function output-enable input. See function table for normal-mode logic.
TCK
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDO
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS input directs the device through its
TAP controller states. An internal pullup forces TMS to a high level if left unconnected.
VCC
1D–8D
Supply voltage
Normal-function data inputs. See function table for normal-mode logic.
1Q–8Q
Normal-function data outputs. See function table for normal-mode logic.
P
相關(guān)PDF資料
PDF描述
SN74ABT8373 Scan Test Devices With Octal D-Type Latches(掃描測(cè)試裝置(帶八D鎖存器))
SN54ABT8374 Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測(cè)試裝置(帶八D邊沿觸發(fā)器))
SN74ABT8374 Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測(cè)試裝置(帶八D邊沿觸發(fā)器))
SN54ABT845 Octal Bus Interface D-Type Latches With 3-State Outputs(八總線接口D鎖存器(三態(tài)輸出))
SN74ABT845 Octal Bus Interface D-Type Latches With 3-State Outputs(八總線接口D觸發(fā)器(三態(tài)輸出))
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