- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373435 > SN54ABT8373 (Texas Instruments, Inc.) Scan Test Devices With Octal D-Type Latches(掃描測試裝置(帶八D鎖存器)) PDF資料下載
參數(shù)資料
| 型號： | SN54ABT8373 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With Octal D-Type Latches(掃描測試裝置(帶八D鎖存器)) |
| 中文描述： | 掃描測試設(shè)備與八路D類鎖存器（掃描測試裝置（帶八?鎖存器）） |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 391K |
| 代理商： | SN54ABT8373 |
SN54ABT8373, SN74ABT8373
SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SCBS487 – JULY 1994
3–13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the device input pins is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output pins on each falling edge of TCK. Figure 6 illustrates the
8-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial
seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does
not produce additional patterns.
=
=
M
8D
8Q
7D
6D
5D
4D
3D
2D
1D
7Q
6Q
5Q
4Q
3Q
2Q
1Q
Figure 6. 8-Bit PSA/PRPG Configuration
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the device input pins is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit binary count-up
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output pins on each falling edge of TCK. Figure 7 illustrates the
8-bit linear-feedback shift-register algorithm through which the signature is generated. An initial seed value
should be scanned into the BSR before performing this operation.
=
=
M
8D
8Q
7D
6D
5D
4D
3D
2D
1D
7Q
6Q
5Q
4Q
3Q
2Q
1Q
MSB
LSB
Figure 7. 8-Bit PSA/COUNT Configuration
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ABT8373 | Scan Test Devices With Octal D-Type Latches(掃描測試裝置(帶八D鎖存器)) |
| SN54ABT8374 | Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測試裝置(帶八D邊沿觸發(fā)器)) |
| SN74ABT8374 | Scan Test Devices With Octal D-Type Edge-Triggered Flip-Flops(掃描測試裝置(帶八D邊沿觸發(fā)器)) |
| SN54ABT845 | Octal Bus Interface D-Type Latches With 3-State Outputs(八總線接口D鎖存器(三態(tài)輸出)) |
| SN74ABT845 | Octal Bus Interface D-Type Latches With 3-State Outputs(八總線接口D觸發(fā)器(三態(tài)輸出)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54ABT841 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT841W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ABT843 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。