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| 型號： | SPAKDSP321VL240 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 10/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 240MHZ 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 240MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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DSP56321 Technical Data, Rev. 11
1-12
Freescale Semiconductor
Signals/Connections
1.9 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals
such as modems.
SCK1
PD3
Input/Output
Input or Output
Ignored Input
Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a
clock input or output used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port D 3—The default configuration following reset is GPIO input PD3. When
configured as PD3, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SCK1 through the Port
D Control Register.
SRD1
PD4
Input
Input or Output
Ignored Input
Serial Receive Data—Receives serial data and transfers the data to the ESSI
Receive Shift Register. SRD1 is an input when data is being received.
Port D 4—The default configuration following reset is GPIO input PD4. When
configured as PD4, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SRD1 through the
Port D Control Register.
STD1
PD5
Output
Input or Output
Ignored Input
Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD1 is an output when data is being transmitted.
Port D 5—The default configuration following reset is GPIO input PD5. When
configured as PD5, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal STD1 through the Port
D Control Register.
Notes:
1.
In the Stop state, the signal maintains the last state as follows:
If the last state is input, the signal is an ignored input.
If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2.
The Wait processing state does not affect the signal state.
Table 1-13.
Serial Communication Interface
Signal Name
Type
State During
Reset1,2
Signal Description
RXD
PE0
Input
Input or Output
Ignored Input
Serial Receive Data—Receives byte-oriented serial data and transfers it to the
SCI Receive Shift Register.
Port E 0—The default configuration following reset is GPIO input PE0. When
configured as PE0, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal RXD through the Port E
Control Register.
TXD
PE1
Output
Input or Output
Ignored Input
Serial Transmit Data—Transmits data from the SCI Transmit Data Register.
Port E 1—The default configuration following reset is GPIO input PE1. When
configured as PE1, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal TXD through the Port E
Control Register.
Table 1-12.
Enhanced Serial Synchronous Interface 1 (Continued)
Signal Name
Type
State During
Reset1,2
Signal Description
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