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| 型號(hào)： | SPAKDSP321VL240 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/84頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 240MHZ 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時(shí)鐘速率： | 240MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Enhanced Synchronous Serial Interface 1 (ESSI1)
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
1-11
1.8 Enhanced Synchronous Serial Interface 1 (ESSI1)
STD0
PC5
Output
Input or Output
Ignored Input
Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD0 is an output when data is transmitted.
Port C 5—The default configuration following reset is GPIO input PC5. When
configured as PC5, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal STD0 through the Port
C Control Register.
Notes:
1.
In the Stop state, the signal maintains the last state as follows:
If the last state is input, the signal is an ignored input.
If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2.
The Wait processing state does not affect the signal state.
Table 1-12.
Enhanced Serial Synchronous Interface 1
Signal Name
Type
State During
Reset1,2
Signal Description
SC10
PD0
Input or Output
Ignored Input
Serial Control 0—For asynchronous mode, this signal is used for the receive
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port D 0—The default configuration following reset is GPIO input PD0. When
configured as PD0, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC10 through the Port
D Control Register.
SC11
PD1
Input/Output
Input or Output
Ignored Input
Serial Control 1—For asynchronous mode, this signal is the receiver frame
sync I/O. For synchronous mode, this signal is used either for Transmitter 2
output or for Serial I/O Flag 1.
Port D 1—The default configuration following reset is GPIO input PD1. When
configured as PD1, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC11 through the Port
D Control Register.
SC12
PD2
Input/Output
Input or Output
Ignored Input
Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port D 2—The default configuration following reset is GPIO input PD2. When
configured as PD2, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC12 through the Port
D Control Register.
Table 1-11.
Enhanced Synchronous Serial Interface 0 (Continued)
Signal Name
Type
State During
Reset1,2
Signal Description
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