- 您現在的位置：買賣IC網 > PDF目錄19294 > SPAKDSP321VL240 (Freescale Semiconductor)IC DSP 24BIT 240MHZ 196-MAPBGA PDF資料下載
參數資料
| 型號： | SPAKDSP321VL240 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 23/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 240MHZ 196-MAPBGA |
| 標準包裝： | 2 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 240MHz |
| 非易失內存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
iii
Features
Table 1 lists the features of the DSP56321 device.
Table 1. DSP56321 Features
Feature
Description
High-Performance
DSP56300 Core
275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering
applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24
× 24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
test access port (TAP)
Enhanced Filter
Coprocessor (EFCOP)
Internal 24
× 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
Operation at the same frequency as the core (up to 275 MHz)
Support for a variety of filter modes, some of which are optimized for cellular base station applications:
Real finite impulse response (FIR) with real taps
Complex FIR with complex taps
Complex FIR generating pure real or pure imaginary outputs alternately
A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
Direct form 2 (DFII) IIR filter
Four scaling factors (1, 4, 8, 16) for IIR output
Adaptive FIR filter with true least mean square (LMS) coefficient updates
Adaptive FIR filter with delayed LMS coefficient updates
Internal Peripherals
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
相關PDF資料 |
PDF描述 |
|---|---|
| VE-B6R-CY-S | CONVERTER MOD DC/DC 7.5V 50W |
| EMC07DRXS | CONN EDGECARD 14POS DIP .100 SLD |
| ACC35DREH-S734 | CONN EDGECARD 70POS .100 EYELET |
| XC5VLX110-1FFG676C | IC FPGA VIRTEX-5 110K 676FBGA |
| VI-BNB-CY-S | CONVERTER MOD DC/DC 95V 50W |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SPAKDSP321VL275 | 功能描述:IC DSP 24BIT 275MHZ 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:DSP56K/Symphony 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| SPAKDSP56824BU70 | 制造商:Freescale Semiconductor 功能描述: |
| SPAKF56009FJ81 | 制造商:Motorola Inc 功能描述: |
| SPAKMC331CFC16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:User’s Manual |
| SPAKMC331CFC20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:User’s Manual |
發(fā)布緊急采購，3分鐘左右您將得到回復。