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| 型號： | SPEAR-07-NC03 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 |
| 封裝： | LEAD FREE, 12 X 12 MM, 1.70 MM HEIGHT, LFBGA-180 |
| 文件頁數(shù)： | 133/194頁 |
| 文件大?。?/td> | 1987K |
| 代理商： | SPEAR-07-NC03 |
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SPEAR-07-NC03
6 Blocks description
43/194
COLL_SEEN
: When '1' the Late Collision seen condition, reported by the MAC110 in the RX
packet status word, will make the received frame to be discharged by the DMA_MAC, without
any report to the CPU.
When '0' no action will be taken by the DMA_MAC.
RUNT_FRAME
: When '1' the Damaged Frame condition (e.g. normal collision, frame too short,
etc.), reported by the MAC110 in the RX packet status word, will make the received frame to be
discharged by the DMA_MAC, without any report to the CPU.
When '0' no action will be taken by the DMA_MAC.
FILTER_FAIL
: When '1' the Address Filtering Failed condition, reported by the MAC110 during
the RX packet transmission, will make the received frame to be discharged by the DMA_MAC,
without any report to the CPU.
When '0' no action will be taken by the DMA_MAC.
If this bit is set the data of packets that don't match the address filtering process (inside the
MAC core) are not moved to the memory reducing the AHB bus utilization.
START_FETCH
: This bit is a Read/Set bit, that means it can be both read and written, but
writing a '0' has no effect.
The SW has to set this bit to '1' when the RX DMA has to start fetching the first descriptor.
The DMA logic will reset to '0' this bit and set the DMA_EN to '1' as soon as the first fetch has
been completed.
Note:
Before starting the DMA, the DMA_NXT register has to be loaded with the starting address of
the descriptor to be fetched.
DMA_EN
: Read/Clear bit: a write with '1' reset to '0' the bit value, while a write with '0' has no
effect.
This bit, set to '1' by the DMA after the first descriptor fetch, can be reset to '0' by the SW to
force a DMA abort and stop as soon as possible the data transfer, before the DMA completion.
When all the DMA sequences complete normally, this bit is reset by the DMA_MAC logic and a
new SW intervention is required to restart the DMA engine.
Note:
●
The DMA_EN 0->1 transition resets the FIFO content and the RX interrupts
(DMA_INT_STAT(15:0)).
●
The DMA_EN 1->0 transition forces the DMA to close immediately the transfers toward
AHB bus and MAC core. When the AHB transfer completes the
DMA_INT_STAT.RX_DONE interrupt is set and the processor can reprogram and
reactivate the RX logic.
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