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| 型號： | SPEAR-07-NC03 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 |
| 封裝： | LEAD FREE, 12 X 12 MM, 1.70 MM HEIGHT, LFBGA-180 |
| 文件頁數(shù)： | 45/194頁 |
| 文件大?。?/td> | 1987K |
| 代理商： | SPEAR-07-NC03 |
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SPEAR-07-NC03
6 Blocks description
139/194
Initially the row address is output and the MISA (RAS) and MICS outputs are asserted. During
the Access state the column address is output on the address bus and the MIAA (CAS) output
is asserted. When the memory access has completed the MIAA and MIWE outputs are
asserted to pre-charge the accessed SDRAM bank.
The SDRAM data accesses are not performed as a single burst. In each access cycle a new
read/write command is issued to the SDRAM device, causing the column address to reload. To
support this mode of operation, the SDRAM device must be configured to have a burst length of
one. Using a number of individual accesses allows the same location to be accessed in a
number of consecutive access cycles e.g. during a byte burst access to a word wide memory
bank.
A SDRAM access is not permitted to cross a 512 byte boundary (the minimum supported
SDRAM row size) without passing through the SETUP cycle to update the SDRAM row
address. After the last access cycle of every transfer, the pre-charge command must be issued
to the SDRAM.
A feature of SDRAM read accesses is that there is some latency between the read access
being initiated and the data being returned by the device. The data latency from the read
command to the first valid data must be configured by the user.
The memory interface is compatible with the Intel "PC SDRAM Specification" and only uses
commands defined in that specification.
6.7.2.2 EDO Access
An EDO access is shown in Figure 17.
Figure 17. EDO Access Example
To support EDO accesses an ADDRESS SETUP cycle has been added to provide a cycle of
setup between the Row address output becoming valid and the RAS signal being activated.
Also added is an ACCESS WAIT cycle, after each ACCESS cycle.
The MICS output is used as the EDO RAS signal.
The DRAM Controller must capture read data on the clock following the read access. The user
must configure the single cycle data latency.
CLK
State
DATA
ADDR
WE/OE
CAS
RAS
Row
Col0
Col15
Idle
CLK
State
DATA
ADDR
WE/OE
CAS
RAS
Row
Col0
Col15
Idle
Access
Wait
Idle
Access
Wait
Idle
Col1
Address
setup
Setup
Access
wait
Access
wait
Access
Col1
Address
setup
Setup
Access
wait
Access
wait
Access
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