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| 型號(hào)： | SPEAR-07-NC03 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 |
| 封裝： | LEAD FREE, 12 X 12 MM, 1.70 MM HEIGHT, LFBGA-180 |
| 文件頁(yè)數(shù)： | 22/194頁(yè) |
| 文件大?。?/td> | 1987K |
| 代理商： | SPEAR-07-NC03 |
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6 Blocks description
SPEAR-07-NC03
118/194
ECP Address FIFO Register (ECPAFIFO)
The ECPAFIFO register provides a channel address to the peripheral depending on the state of
bit 7. This I/O address location is only used in ECP Mode (ECR bits [7:5]=011). In this mode,
bytes written to this register are placed in the parallel port FIFO and transmitted via
PDOUT[7:0] using the ECP protocol. Bit 7 should always be set to 1.
Bits [7:0] ECP Address
The register contents is passed to the peripheral by PDOUT[7:0]. The peripheral should
interpret bits [6:0] as a channel address.
Note:
that the SPEAr Net asserts NAUTOFD to indicate that information on the PD[7:0] is an ECP
address. The SPEAr Net negates NAUTOFD when PD[7:0] is transferring data.
Status Register (STAT)
Already discussed in Section 5.4.5.1.1.
Control register (CTRL)
Already discussed in Section 5.4.5.1.2.
Standard Parallel Port Data FIFO Register (SDFIFO)
SDFIFO is used to transfer data from the host to the peripheral when the ECR register is set for
compatible FIFO mode (Bits [7:5] = 010). Data bytes written or DMAed from the system to this
FIFO are transmitted by a hardware handshake to the peripheral using the standard
Compatibility protocol.
For this register, bytes are placed in the parallel port FIFO using DATAIN[7:0] and transmitted
via PDOUT[7:0].
Note:
that bit 5 in the CTRL register must be set to 0 for forward transfer.
ECP Data FIFO Register (ECPDFIFO)
ECPDFIFO is used to transfer data from the host to the peripheral when the ECR register is set
for ECP mode (Bits [7:5] = 011). Data bytes written or DMAed from the system to this FIFO are
transmitted by a hardware handshake to the peripheral using the ECP protocol.
Note:
that bit 5 in the CTRL register must be set to 0 for forward transfer or to 1 for a reverse transfer.
Test FIFO Register (TFIFO)
The Test FIFO provides a test mechanism for the ECP Mode FIFO by allowing data to be read,
written or DMAed in either direction between the system and this FIFO. This Test Mode is
selected by setting ECR[7:5] = 110.
The data is transferred purely through the microprocessor interface and is therefore transferred
at the maximum ISA rate.
It may appear on the parallel port data lines, but without any hardware handshake.
The Test FIFO does not stall when overwritten or under-run. Data is simply ignored or re-read.
The full and empty bits of the ECR register (bits 1 and 0) can however be used to ascertain the
correct state of the FIFO.
ECP Configuration Register A (CFGA)
The CFGA register provides information about the ECP Mode implementation. It is a Read Only
register. Access to this register is enabled by programming the ECR register (ECR[7:5] = 111).
The bit definitions in this register are shown below:
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