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| 型號： | SPEAR-07-NC03 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 |
| 封裝： | LEAD FREE, 12 X 12 MM, 1.70 MM HEIGHT, LFBGA-180 |
| 文件頁數(shù)： | 42/194頁 |
| 文件大小： | 1987K |
| 代理商： | SPEAR-07-NC03 |
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6 Blocks description
SPEAR-07-NC03
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6.6.4.2 Master Mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition and Transmit Slave address
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
–
The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register with
the Slave address byte, holding the SCL line low (see Figure 8 Transfer sequencing EV5).
Then the slave address byte is sent to the SDA line via the internal shift register.
After completion of this transfers (and acknowledge from the slave if the ACK bit is set):
–
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register (for
example set PE bit), holding the SCL line low (see Figure 8 Transfer sequencing EV6).
Next the master must enter Receiver or Transmitter mode.
Master Receiver
Following the address transmission and after SR1 and CR registers have been accessed, the
master receives bytes from the SDA line into the DR register via the internal shift register. After
each byte the interface generates in sequence:
–
Acknowledge pulse if if the ACK bit is set
–
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 8 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP bit
to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge pulse after the last received data byte, the
ACK bit must be cleared just before reading the second last data byte.
Master Transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 8 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets:
–
EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
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