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| 型號： | SPEAR-07-NC03 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 |
| 封裝： | LEAD FREE, 12 X 12 MM, 1.70 MM HEIGHT, LFBGA-180 |
| 文件頁數(shù)： | 158/194頁 |
| 文件大?。?/td> | 1987K |
| 代理商： | SPEAR-07-NC03 |
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6 Blocks description
SPEAR-07-NC03
Transfer Interrupts
The DMA MAC can interrupt the CPU with three different levels of information about transfer
completion. The CPU can choose which interrupt needs to be enabled. They do not exclude
each other though; they can be all three enabled at the same time.
The TX_CURR_DONE (RX_CURR_DONE) interrupt bit reports the CPU when a single
Descriptor (i.e. one frame) has been completely treated by the DMA MAC and the CPU is again
the owner (VALID bit is set to 0).
The TX_NEXT (RX_NEXT) interrupt bit is set when next descriptor fetch is enabled (NXT_EN
set to 1 in the current Descriptor) but the next Descriptor is not valid (Valid bit is set to 0).
The TX_DONE (RX_DONE) interrupt bit is set when a whole DMA transfer is complete. This
can happens either when the current is the last Descriptor in the chain (NXT_EN is set to 0) or
when the next Descriptor is not valid yet (VALID bit set to 0) and the polling bit is disabled
(NPOL_EN set to 0).
6.2.5.5 Frame Transmission (Tx)
When the CPU wants to transmit a set of frames on the cable, it needs to provide the DMA
MAC with a Descriptor list. The CPU is expected to allocate a Descriptor for each frame it wants
to send, to fill it with the DMA control information and the pointer to the frame and to link the
Descriptor in the chain (see Figure 6). The frames will be sent on the cable in the same order
they are found on the chain.
6.2.5.6 Open list approach
The simplest way to construct a Descriptor chain is the open list approach. Every Descriptor but
the last one will have the DMA_NEXT field pointing to the next descriptor in the chain, the
NXT_EN bit and the VALID bit on, the NPOL_EN bit on or off. The last Descriptor will e set in
the same way except for the NXT_EN bit (off) and the DMA_NEXT field (NULL).
The CPU starts the DMA activity loading the physical location of the first Descriptor into the
DMA_NEXT Register of the DMA MAC and then set the DMA_START resister enable bit to on.
The DMA MAC will then keep fetching the Descriptors one by one until it finds the NXT_EN bit
set to off (last Descriptor in the chain). Every time it completes a descriptor (frame) it saves the
transfer status into TxRx_STATUS, it turns the Descriptor VALID bit to off and rises the
TX_CURR_DONE interrupt bit.
When the NXT_EN bit is found to be off, that means the DMA MAC has fetched the last
Descriptor in the chain. When it completes also this Descriptor (the end of the DMA transfer) it
raises both the TX_CURR_DONE and the TX_DONE interrupt bits.
Closed list approach
The approach above is easy since it doesn't require the DMA MAC and the CPU to synchronize
their access to the descriptor chain. The problem is that requires the CPU to build the list every
time it needs a transfer.
A faster way to operate is building a closed Descriptor list only the first time and using the
VALID bit to mark the end of the transfer. Even more the polling facility could be used to save
the CPU from the activity of programming the DMA_START register every time it needs to start
the DMA Transfer. Instead, the DMA_START register will be activated only once and the DMA
MAC will keep polling the invalid Descriptor, raising each time the TX_NEXT interrupt bit (if
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