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參數(shù)資料
| 型號： | ST7267R8T1L/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 125/189頁 |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7 INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
When an event occurs on an I/O port, this incom-
ing signal is interpreted as an external interrupt.
This signal can also be used to wake up the De-
vice from HALT. There are several controlling fac-
tors for external interrupts:
– Priority (Hardware and Software)
– Enable/Disable control bits
– Sensitivity Control
– Status Flag
Up to 8 signals on 8 ports can share one external
interrupt. For example, ei0 is shared on all 8 ports
of Port A.
7.6.1 Software and Hardware Priorities
External interrupts have default priorities associat-
ed with them. They are as listed in the Interrupt
Mapping table. These are the hardware priorities
and are unchangeable.
Software priorities are user assigned by program-
ming the appropriate bits in the Interrupt Software
Priority register (ISPRx) for a given external inter-
rupt. The whole external interrupt group will have
the same priority. For example, ISPR1 bits[0:1]
control the software priority for Port A’s external in-
terrupt, ei0.
These two types of priorities are important to man-
age because they function in the same manner as
other interrupts for concurrent and nested modes.
7.6.2 Enable and Sensitivity Controls
At an external interrupt event, for the interrupt to
be acknowledged, it must be enabled. There is a
control bit for each external interrupt. They are
found in the External Interrupt Enable Port x regis-
ter (PxEINENR).
The external interrupt sensitivity is controlled by
the ISxx bits in the EICRx registers (Figure 18).
This control allows to have up to 4 fully independ-
ent external interrupt source sensitivities.
Each external interrupt source can be generated
on four different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3).
7.6.3 Status Flag
When an event occurs signalling that an external
interrupt is requested, a flag is set by hardware.
This flag informs the user which external interrupt
has occurred. Each external interrupt has its own
specific flag. They are found in the External Inter-
rupt Port x register (PxEISR). If the corresponding
external interrupt is enabled when this flag is set,
the external interrupt is serviced.
If several interrupts are pending, the interrupts are
serviced according to their priority (software and or
hardware, according to which interrupt mode is be-
ing employed).
If there is an unwanted pending interrupt, it can be
cleared by writing a different value in the ISx[1:0]
in the EICRx registers.
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