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| 型號(hào)： | ST7267R8T1L/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件頁(yè)數(shù)： | 28/189頁(yè) |
| 文件大小： | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7267C8 ST7267R8
123/189
15 MSCI I/O CONTROLLER
15.1 Introduction
The MSCI I/O ports can be configured in different
functional modes:
- data transfer through digital inputs and outputs
and for specific pins:
- alternate input/output signals for the parallel in-
terface.
Each of the two I/O ports contains 16 pins. Each
pin can be programmed independently as digital
input or digital output.
15.2 Functional Description
Each port has 3 main registers:
- Data Register Out (DRO)
- Data Register Input (DRI)
- Data Direction Register (DDR)
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR register: bit X
corresponding to pin X of the port. The same cor-
respondence is used for the DRO and DRI regis-
ters.
The DRO and DDR registers can be read and writ-
ten by the MSCI core. The DRI register is an im-
age corresponding to the logic level on the I/OO
pin and can be read by the MSCI core (read only
register).
The MSCI I/O control block diagram is shown in
15.2.1 Input mode
The input configuration is selected by clearing the
corresponding DDR register bit. In this case, read-
ing the DRI register returns the digital value ap-
plied to the external I/O pin.
In this mode writing the DRO register has no effect
on the pad. However the values are written in the
DRO register and if the DDR register is set to out-
put mode, the value on the port will be the value
written previously in the DRO register.
15.2.2 Output mode
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DRO register applies this digital value to
the I/O pin through the latch.
In this mode reading the DRI register returns the
digital value applied to the external I/O pin.
15.2.3 Alternate functions
When an on-chip peripheral is configured to use a
pin in output mode, the alternate function is auto-
matically selected. This alternate function takes
priority over the standard I/O programming.
When the signal is coming from the parallel inter-
face, the I/O pin is automatically configured in out-
put mode when needed. There are two cases de-
pending of the type of signal:
- Control signals are configured using the CS bit in
the PCR2 register.
- Data signals are configured when the DIR bit in
the PCR1 register is set in output mode and data
transmission is on going.
When the signal is going to the parallel interface
(input mode), the I/O pin has to be configured in in-
put mode by the standard I/O programming to
avoid conflicts.
Figure 51. I/O Port General Block Diagram (When I/Os are dedicated to MSCI)
DRO
DDR
DA
TA
B
U
S
VDD
ALTERNATE
OUTPUT
1
0
DDR SEL
DRI SEL
PULL-UP
CONDITION
P-BUFFER
N-BUFFER
VDD
CMOS
SCHMITT
TRIGGER
DRO SEL
ALTERNATE
ENABLE
PAD
I/O
MSCI I/O Controller
MSCI CLOCK
1
0
VDD
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