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參數(shù)資料
| 型號： | ST7267R8T1L/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 3/189頁 |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7267C8 ST7267R8
100/189
Bit 6:5 = Reserved.
Bit 4 = DMAE DMA Enable
0: DMA request for the IN endpoint disabled
1: DMA request for the IN endpoint enabled.
Bit 3 = FDT Force Data Toggle
The CPU sets this bit to force the endpoint’s IN
data toggle to switch after each data packet is sent
regardless of whether an ACK was received.
0: Data toggle not forced
1: Data toggle forced
Bits 2:0= Reserved.
IN CONTROL STATUS REGISTER LSB (INCS-
RL)
INCSRL is the LSB of a register that provides con-
trol and status bits for IN transactions through the
currently-selected endpoint. There is an INCSRL
register for each IN endpoint (not including End-
point 0). For endpoint 0 this control status register
is common to SETUP, IN or OUT transactions.
For endpoint 0 (CSR0):
CSR0 appears in the memory map when the Index
register is set to 0. It is used for all control/status of
Endpoint 0. For details of how to service device re-
quests to Endpoint 0, see Section 12.4.10: ‘End-
point 0 Handling’.
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = SSE Serviced Setup End.
Software writes a 1 to this bit to clear the SE bit.
SSE is cleared automatically.
Bit 6 = SOPR Serviced OUT Packet Ready.
Software writes a 1 to this bit to clear the OPR bit.
SOPR is cleared automatically
Bit 5 = SDST Send Stall.
Software writes a 1 to this bit to terminate the cur-
rent transaction. The STALL handshake will be
transmitted and then this bit will be cleared auto-
matically.
Bit 4 = SE Setup End (Read Only)
This bit will be set when a control transaction ends
before the DE bit has been set. An interrupt will be
generated and the FIFO flushed at this time. The
bit is cleared by software writing a 1 to the SSE bit.
Bit 3 = DE Data End
Software sets this bit:
- when setting IPR bit for the last data packet.
- when clearing OPR bit after unloading the last
data packet.
- when setting IPR bit for a zero length data pack-
et.
It is cleared automatically.
Bit 2 = STST Sent Stall
This bit is set when a STALL handshake is trans-
mitted. The CPU should clear this bit.
Bit 1 = IPR In Packet Ready
Software sets this bit after loading a data packet
into the FIFO. It is cleared automatically when the
data packet has been transmitted. An interrupt is
generated when the bit is cleared.
Bit 0 = OPR Out Packet Ready (Read Only)
This bit is set when a data packet has been re-
ceived. An interrupt is generated when this bit is
set. Software clears this bit by setting the SOPR
bit.
For endpoint 1 and 2:
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = Reserved.
Bit 6 = CDT Clear Data Toggle.
Software writes a 1 to this bit to reset the endpoint
IN data toggle to 0.
Bit 5 = STST Sent Stall
This bit is set when a STALL handshake is trans-
mitted. The FIFO is flushed and the IPR bit is
cleared. Software should clear this bit.
70
SSE
SOPR
SDST
SE
DE
STST
IPR
OPR
70
0
CDT
STST
SDST
FLFI
UNDR
FINE
IPR
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