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| 型號(hào)： | ST7267R8T1L/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件頁(yè)數(shù)： | 76/189頁(yè) |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7267C8 ST7267R8
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18.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
18.7.1
Functional
EMS
(Electro
Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD33 and VSS33
through a 100pF capacitor, until a functional
disturbance occurs. This test conforms with the
IEC 1000-4-4 standard.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
18.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
18.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Notes:
1. Data based on characterization results, not tested in production.
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any
I/O pin to induce a functional dis-
turbance
For LQFP64 (10x10), VDD33=3.3V, TA=+25°C, fOSC=12MHz
conforms to IEC 1000-4-2
4B
VFFTB
Fast transient voltage burst limits
to be applied through 100pF on
VDD33 and VSS33 pins to induce a
functional disturbance
For LQFP64 (10x10), VDD33=3.3V, TA=+25°C, fOSC=12MHz
conforms to IEC 1000-4-4
4A
Symbol
Parameter
Conditions
Monitored
Frequency Band
Max vs. [fOSC/fCPU]
Unit
12/15MHz 12/30MHz
SEMI
Peak level
VDD33=3.3V, TA=+25°C,
LQFP64 10x10 package
conforming to SAE J 1752/3
Note: Refer to Application Note
AN1709 for data on other package
types.
0.1MHz to 30MHz
16
20
dB
V
30MHz to 130MHz
21
25
130MHz to 1GHz
27
25
SAE EMI Level
4
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