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參數(shù)資料
| 型號： | ST7267R8T1L/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 6/189頁 |
| 文件大小： | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7267C8 ST7267R8
103/189
Bits 7:5 = Reserved.
Bit 4:0= OC[12:8] OUT Count.
OUT COUNT REGISTER LSB (OUTCNTRL)
Read/Write
Reset value: 0000 0000 (00h)
OUTCNTRL is the LSB register that holds the
number of received data bytes in the packet in the
OUT FIFO.
Notes:
■ The value returned changes as the contents of
the FIFO change and is only valid while OPR bit
in the OUTCSRL register is set.
■ For endpoint 0 and 1 only OUTCNTRL has to be
read (OUTCNTRM is reserved and returns
00h).
Bits 7:0 = OC[7:0] OUT Count.
10.5.6.3 FIFO register addressing
This address range provides 3 addresses for CPU
access to the FIFOs for each endpoint. Writing to
these addresses loads data into the IN FIFO for
the corresponding endpoint. Reading from these
addresses unloads data from the OUT FIFO for
the corresponding endpoint.
10.5.6.4 End of suspend detection register
This register controls a specific end of suspend
block that is able to wake-up the ST7 when the
clocks are stopped.
EOS STATUS REGISTER (EOSSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = LS1 Line State 1 flag.
This bit is read only by software
0: LS1 is at 0 (D-=0)
1: LS1 is at 1 (D-=1)
Bit 6 = LS0 Line State 0 flag.
This bit is read only by software
0: LS0 is at 0 (D+=0)
1: LS0 is at 1 (D+=1)
Bit 5:1 = Reserved.
Bit 0 = EOS End Of Suspend.
This bit is set by hardware and cleared by soft-
ware.
0: No EOS interrupt occurred
1: EOS interrupt occurred
Note:
A parasitic EOS bit set can occur at device start up
so it is mandatory to clear this bit before enabling
the interrupt (by setting EOSE).
EOS CONTROL REGISTER (EOSCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = LSE Line State Enable.
This bit is set and cleared by software.
0: Line State flag disabled
1: Line State flag enabled.
Bit 6:3 = Reserved.
Bit 2 = UPO USB2 Phy Off.
This bit is set and cleared by software. When the
USB part is not used the PHY can be stopped
completely to remove useless consumption.
0: USB2 PHY enabled
1: USB2 PHY disabled.
Bit 1 = CPO Compensation Cell Off.
This bit is set and cleared by software. Set this bit
to decrease the consumption (for instance before
entering in suspend / halt mode) by removing the
IOs active slew rate control PVT compensation.
70
OC7
OC6
OC5
OC4
OC3
OC2
OC1
OC0
Address
R/W
FIFO accessed
21h
R
Endpoint 0 OUT / SETUP
W
Endpoint 0 IN
23h
R
Endpoint 1 OUT
W
Endpoint 1 IN
25h
R
Endpoint 2 OUT
W
Endpoint 2 IN
70
LS1
LS0
00
000
EOS
70
LSE
0
UPO
CPO
EOSE
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