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參數(shù)資料
| 型號(hào)： | ST7267R8T1L/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件頁(yè)數(shù)： | 49/189頁(yè) |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7267C8 ST7267R8
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MSCI PARALLEL INTERFACE (Cont’d)
17.3 CONFIGURING THE CONTROL LINES
Eight lines are available to provide automatic con-
trol signals output toward external communication
devices. Only one control signal generator is used
to create one control signal that can be output on
eight dedicated I/Os. One output enable signal is
available for each output (bits 4 to 11 of the PCR2
register). If an enable bit is set, the corresponding
I/O is forced to output mode and controlled by the
control signal generator. If the enable signal is re-
set, the corresponding I/O can be controlled by the
MSCI I/O registers.
17.3.1 Control Signal Enable bits
When enabling some control signals by setting the
corresponding CSE bits of the PCR2 register, un-
expected pulse can be observed on I/O when
CLDV value if the port was previously in input
mode or if the port level was not the value chosen
for CLDV.
To avoid an unexpected pulse on the control I/Os
when switching from MSCI I/O controller to parallel
interface control, the following MSCI software se-
quences must be used:
If control I/Os were previously in input mode:
a) Configure CLDV bit of the PCR2 register with
all control lines disabled.
b) Load the MSCI I/O Controller DRO bits corre-
sponding to the control I/O used with the CLDV
value.
c) Select output mode with MSCI I/O controller for
the control line I/O by setting the corresponding
bits of the DDR register.
d) Set the control signal enable bits in the PCR2
register.
If control I/Os were already configured in out-
put mode by MCI I/O logic:
a) Configure CLDV bit of the PCR2 register with
all control lines disabled.
b) Load the MSCI I/O controller DRO bits corre-
sponding to the control I/O used with the CLDV
value.
c) Set the control signals enable bits in the PCR2
register.
17.3.2 Control Signal Parameters
When a communication is started, a pulse is out-
put for each data sent to (or read from) the data I/
Os.
The shape of this pulse can be configured with the
PCR1 and PCR2 registers. The parameters de-
scribed in this chapter must be configured to ob-
tain the desired control signal.
17.3.2.1 Control Line Default Value (CLDV)
CLDV (bit 0 in the PCR2 register) The Control Line
Default Value is the value that is output on ena-
bled control I/Os when communication is not run-
ning.
Figure 58. Effect of CLDV Parameter
communication on going
CLDV=1
CLDV=0
commnunication
not started
commnunication
terminated
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