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| 型號： | T48C893-TKQ |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | The multiple times programmable (MTP) version for the MARC4 ROM types |
| 中文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 29/82頁 |
| 文件大小： | 638K |
| 代理商： | T48C893-TKQ |
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T48C893
Rev. A4, 22-Jan-02
29 (82)
4.3
Universal Timer/Counter / Communication Module (UTCM)
The
U
niversal
T
imer/counter/
C
ommunication
M
odule
(UTCM) consists of three timers (Timer 1 ,Timer 2,
Timer 3) and a
S
ynchronous
S
erial
I
nterface (SSI).
Timer 1 is an interval timer that can be used to
generate periodical interrupts and as prescaler for
Timer 2, Timer 3, the serial interface and the watch-
dog function.
Timer 2 is an 8/12-bit timer with an external clock in-
put (T2I) and an output (T2O).
Timer 3 is an 8-bit timer/counter with its own input
(T3I) and output (T3O).
The SSI operates as two wire serial interface or as shift
register for modulation and demodulation. The
modulator and demodulator units work together with
the timers and shift the data bits into or out of the shift
register.
There is a multitude of modes in which the timers and the
serial interface can work together.
Demodu
–
lator 3
8
–
bit Counter 3
Capture 3
Compare 3/1
Compare 3/2
Modu
–
lator 3
MUX
MUX
Control
Watchdog
Interval / Prescaler
Timer 1
Timer 3
Modu
–
lator 2
4
–
bit Counter 2/1
Compare 2/1
MUX
MUX DCG
8
–
bit Counter 2/2
Compare 2/2
Control
Timer 2
MUX
8
–
bit Shift
–
Register
Receive
–
Buffer
Transmit
–
Buffer
Control
SSI
SCL
INT4
INT5
INT2
NRST
INT3
POUT
TOG2
TOG3
T1OUT
SUBCL
SYSCL
from clock module
T3O
T3I
13765
T2I
T2O
SC
SD
I/O bus
Figure 27. UTCM block diagram
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