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| 型號： | T48C893-TKQ |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | The multiple times programmable (MTP) version for the MARC4 ROM types |
| 中文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 42/82頁 |
| 文件大?。?/td> | 638K |
| 代理商： | T48C893-TKQ |
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T48C893
Rev. A4, 22-Jan-02
42 (82)
4.3.3
Timer 3
Features
2 Compare Registers
Capture Register
Edge sensitive input with zero cross detection capa-
bility
Trigger and single action modes
Output control modes
Automatically modulation and demodulation modes
FSK modulation
Pulse width modulation (PWM)
Manchester demodulation together with SSI
Biphase demodulation together with SSI
Pulse-width demodulation together with SSI
8
–
bit Counter 3
RES
Compare 3/1
T3CO1
T3CP
T3CO2
Control
T3O
CL3
T3I
T3EX
SYSCL
T1OUT
POUT
I/O
–
bus
13808
Compare 3/2
T3CM1
T3CM2
T3C
T3ST
Modulator 3
Demodu
–
lator 3
M2
Control
SO
TOG3
INT5
RES
CM31
T3I
T3EX
TOG2
SI
SCI
T3M
T3CS
I/O
–
bus
Timer 2
SSI
SSI
CP3
Figure 44. Timer 3
Timer 3 consists of an 8-bit up-counter with two compare
registers and one capture register. The timer can be used
as event counter, timer and signal generator. Its output can
be programmed as modulator and demodulator for the
serial interface. The two compare registers enable various
modes
of
signal
generation,
demodulation. The counter can be driven by internal and
external clock sources. For external clock sources, it has
a programmable edge-sensitive input which can be used
as counter input, capture signal input or trigger input. This
timer input is synchronized with SYSCL. Therefore in the
power-down mode SLEEP (CPU core
–
> sleep and OSC
–
Stop
–
> yes) this timer input is stopped too. The counter
is readable via its capture register while it is running. In
capture mode, the counter value can be captured by a
programmable capture event from the Timer 3 input or
Timer 2 output.
modulation
and
A special feature of this timer is the trigger- and single-ac-
tion mode. In trigger mode, the counter starts counting
triggered by the external signal at its input. In single-ac-
tion mode, the counter counts only one time up to the
programmed compare match event. These modes are very
useful for modulation, demodulation, signal generation,
signal measurement and phase controlling. For phase
controlling, the timer input is protected against negative
voltages and has zero-cross detection capability.
Timer 3 has a modulator output stage and input functions
for demodulation. As modulator it works together with
Timer 2 or the serial interface. When the shift register is
used for modulation the data shifted out of the register is
encoded bitwise. In all demodulation modes, the decoded
data bits are shifted automatically into the shift register.
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