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| 型號： | T48C893-TKQ |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | The multiple times programmable (MTP) version for the MARC4 ROM types |
| 中文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 50/82頁 |
| 文件大?。?/td> | 638K |
| 代理商： | T48C893-TKQ |
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T48C893
Rev. A4, 22-Jan-02
50 (82)
Timer 3 Status Register 1 (T3ST) Read
Primary register address:
’
C
’
hex
–
Read
Bit 3
–
–
–
Bit 2
T3ED
Bit 1
T3C2
Bit 0
T3C1
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Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.
T3ST Read
Reset value: x000b
T3ED
This bit will be set when a match occurs between Counter 3 and T3CO2
T
3 E
D
imer
ompare
Timer 3 Clock Select Register (T3CS)
Address:
’
B
’
hex
–
Subaddress:
’
1
’
hex
Bit 3
Bit 2
Bit 1
Bit 0
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T3CS1
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1
1
0
0
–
–
–
Positive edge at T3I pin
Negative edge at T3I pin
Each edge at T3I pin
T
imer
3 C
lock
S
ource select bit
1
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á
á
á
á
á
á
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T3CS0
T
imer
3 C
lock
S
ource select bit
0
T3CS1
TCS0
1
Counter 3 Input Signal (CL3)
System clock (SYSCL)
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1
Timer 3 Compare- and Compare Mode Register
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the
content of the compare register with the current counter value. If both match, it generates a signal. This signal can be
used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock or as clock for
the next counter stage. For each compare register an compare-mode register exists. This registers contain mask bits
to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a
compare match of the corresponding compare register. The mask bits for activating the single-action mode can also
be located in the compare mode registers. When assigned to the compare register a compare event will be supressed.
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