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| 型號： | T48C893-TKQ |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | The multiple times programmable (MTP) version for the MARC4 ROM types |
| 中文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 7/82頁 |
| 文件大?。?/td> | 638K |
| 代理商： | T48C893-TKQ |
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T48C893
Rev. A4, 22-Jan-02
7 (82)
3
3.1
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced
stack-based, 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with
physically separate program memory (ROM) and data
memory (RAM). Three independent buses, the
instruction bus, the memory bus and the I/O bus, are used
for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes both, an expression and a
return stack. This architecture enables high-level
language programming without any loss of efficiency or
code density.
TOS
ALU
RAM
RP
SP
Clock
Reset
Sleep
I/O bus
Instruction
Reset
System
clock
On
–
chip peripheral modules
94 8973
Figure 3. MARC4 core
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