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參數(shù)資料
| 型號： | T9000 |
| 英文描述： | ISDN Network Termination Node (NTN) Device |
| 中文描述： | ISDN網(wǎng)絡終端節(jié)點（新界北）設備 |
| 文件頁數(shù)： | 30/126頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | T9000 |
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30
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
7 Transmission Superblock
(continued)
7.3 Data Flow/Activation Control Module
(DFAC)
This module provides the following functions:
I
S/T-interface and U-interface activation/deactivation
control.
I
U-interface management.
— M4 bit filtering.
— Automatic/manual EOC channel control.
— Register interface.
— Activation/deactivation management.
I
S/T-interface management.
— Register interface.
— Activation/deactivation management.
I
Data flow functions:
— Mapping of B1-, B2-, and D-channel data between
S/T bus and U bus.
— Mapping of D-channel data between the HDLC
transmitter module and the U bus.
— Mapping of B1- and B2-channel data between the
GCI+ interface and the U bus.
7.3.1 EOC State Machine (EOCSM)
EOCSM module processes the downstream EOC. The
received EOC data/message is transferred to the
microcontroller. The upstream EOC channel may
be directly controlled by the microcontroller
(DFCF[AUTOEOC = 0]) or automatically generated
by the EOCSM as shown in Figure 7.
7.3.2 Automatic EOC (AUTOEOC) Mode
In the automatic EOC (AUTOEOC) mode, the down-
stream EOC messages are interpreted and acted upon
by the NTN with no need for microcontroller interven-
tion. The appropriate upstream response is automati-
cally generated.
The set of EOC messages supported by the NTN are
those defined in ETSI TS 080 and
ANSI
T1.601, and
are shown in Table 21.
7.3.3 Manual EOC Mode
In the manual EOC mode, the microcontroller is
responsible for interpreting the downstream EOC mes-
sage, taking the appropriate action, and responding
correctly in the upstream direction.
In both manual and AUTOEOC modes, the NTN stores
the most recent downstream EOC contents in registers
ESR0 and ESR1. The microcontroller can be inter-
rupted on either a single change in the EOC contents
(see bit UIR[EOCSC]) or a trinal-checked change in the
EOC contents (see bit UIR[EOC3SC]). Actions in
response to the standard set of messages shown in
Table 21 can be taken by writing to register ECR0[7:4].
The microcontroller writes the upstream EOC response
to registers ECR0[3:0] and ECR1[7:0]. The half-super-
frame interrupt UIR[RHSF] can be used to determine
the correct EOC message timing.
All actions are latched, permitting multiple EOC-initi-
ated actions to be in effect simultaneously. The transi-
tion of transmission system through either receiver
reset or full reset states releases all the outstanding
EOC-controlled operations, and resets the EOC pro-
cessor to return-to-normal.
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