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參數(shù)資料
| 型號： | T9000 |
| 英文描述： | ISDN Network Termination Node (NTN) Device |
| 中文描述： | ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界北）設(shè)備 |
| 文件頁數(shù)： | 69/126頁 |
| 文件大小： | 2127K |
| 代理商： | T9000 |
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Lucent Technologies Inc.
69
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
T9000
10 GCI+ Interface Module
The programmable GCI+ interface supports a large variety of codec interfaces, including GCI, long-frame sync
(LFS) TDM, and short-frame sync (SFS) TDM; hence, the + attribute. These interfaces cover most available
codecs on the marketplace (Lucent, Siemens National*, and Motorola
).
The GCI+ interface is comprised of seven signals as shown in Table 77. The pin routing of the FSC and PFS1 sig-
nals changes slightly depending on whether the device is in TDM or GCI mode. This was done in order to place the
signal most likely to be used in each mode on the FS1 pin rather than the GPIO2.2 pin. This allows the GPIO2.2
signal to be available for other uses in most cases.
Table 77. GCI+ Interface Signals
The GCI+ interface behavior depends on the operational mode defined by its configuration register, GCCF. Three
modes are supported by the GCI+ interface:
I
GCI-NT mode (GCCF[GMODE(1:0)] = 00).
I
GCI-TE mode (GCCF[GMODE(1:0)] = 01).
I
TDM mode (GCCF[GMODE(1:0)] = 1x).
10.1 TDM Mode (GCCF, GMODE[1:0] = 1x)
TDM mode is for use with codecs having a simple TDM interface. Figure 13 and Figure 14 show the timing for the
GCI+ interface when programmed in TDM mode.
There are two clock modes for the data clock, DCL: single clock and double clock mode. In single clock mode
(GCCF[CKMODE] = 1), there is one DCL cycle per bit. In double clock mode (GCCF[CKMODE] = 0), there are two
DCL cycles per bit. The DCL clock rate is programmed via the GCCF[GRATE(1:0)] register bits. The DCL rates
supported in TDM mode are 512 kHz, 1536 kHz, or 2048 kHz. Since there can be either one or two DCL cycles per
data bit, depending on whether the GCI+ is in single or double clock mode, there are six possible data rates, as
shown in Table 78. In addition, a powerdown mode is available in which DCL is stopped (see Section 10.5, GCI+
Powerdown Mode).
In double clock mode, a bit clock (BCLK) signal is available on the GPIO2.1 pin when GPAF1[GPAF2.1] = 1. BCLK
occurs once per bit time and is a divide-by-two version of the DCL signal. BCLK is always 0 in single clock mode.
* National
is a registered trademark of National Semiconductor Corporation
.
Motorola
is a registered trademark of Motorola, Inc.
Function
Name
FSC
PFS1
PFS2
DCL
BCLK
DU
DD
GCI Pin
TDM Pin
I/O
Meaning
FS1
GPIO2.2
FS1
FS2
DCL
GPIO2.1
DU
DD
O
O
O
O
O
I
O
Reference frame sync (marks start of frame).
Programmable frame sync 1 (marks location of B1 channel).
Programmable frame sync 2 (marks location of B2 channel).
Data clock (defined with GRATE bits).
Bit clock (only active during 2 times data clock mode).
Data upstream (U transmit data).
Data downstream (U receive data).
GPIO2.2
FS2
DCL
GPIO2.1
DU
DD
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